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Data Sheet ADP5587

Rev. D | Page 9 of 24

To prevent glitches or narrow press times registering as valid

key presses, the key scanner requires the key to be pressed for

two scan cycles. The key scanner has a sampling period of 25 ms;

therefore, the key must be pressed and held for at least 25 ms to

scanner continues to sample every 25 ms. If a pressed key is

released for 25 ms or greater, the state machine sets the

appropriate key number in the key event status register with the

key-pressed bits cleared in the order detected. Because the

release of a key is not necessarily in sync with the key scan

sampling period, it may take between 25 ms and 50 ms for a key

to register as released. After the key is registered as released, the

key scanner returns to idle mode. Figure 10 shows the row and

column pins connected to a typical 10 × 8, 80-switch keypad

matrix.

KEYPAD SCAN AND DECODE

D0_PULL

R7 R6 R5 R4 R3 R2 R1

C0 C1 C2 C3 C4 C5 C6 C7 C9C8

10 × 8 KEYPAD MATRIX

D1_PULL

D2_PULL

D3_PULL

D4_PULL

D5_PULL

D6_PULL

D7_PULL

08612-006

NOTES:

1. Dx_PULL STANDS FOR GPIO PULL-UP.

Figure 10. Keypad Decode Configuration

Key Event Tracking

The 10 key event registers are set to act as a FIFO, meaning that

reading any of the 10 key event registers yields the key events in

the order the keys were pressed and released.

Tracking of key events is done with the help of the key event

counter (the KEC field in Register 0x03) and the FIFO/key

event registers (Register 0x04 through Register 0x0D). The KEC

count increases as keys are pressed and released; up to 10 events

can be logged in the counter. The FIFO/key event registers, on

the other hand, display the key events and their status (pressed

or released) as they are read out of the FIFO. The FIFO registers

contain eight bits, with the MSB dedicated as the status bit (1

indicates a press and 0 indicates a release); the remaining seven

bits display the binary representation of the keys that are pressed

or released.

The first read of any of the FIFO registers displays the first

event that happened and its status. Subsequent reads of the

same register replace the register data with the next event that

happens. If tracking of all the events is important, it is best to

use a single register per event. After all the events in the FIFO

are read, reading of any of the event registers yields a zero value.

Table 10 and Table 11 show the event sequences as they are

logged in and read from the FIFO. The 10 FIFO registers are

labeled A through J, and the keys are labeled A0 through J7.

Table 10. Example of Event Sequence

Key Pressed/Released Status Key Event Counter

A0 Pressed 1

Pressed

A0 Released 3

C2 Pressed 4

B1 Released 5

D3 Pressed 6

C2 Released 7

E4 Pressed 8

E4 Released 9

D3 Released 10

Table 11. Interpretation of FIFO Event Reading

Key Event

Counter

Key Event

Read

Key Event Reg-

ister Content

(Binary)

Key Event

Interpretation

10 N/A N/A N/A

9 D 1 0000001 Key A0 pressed

8 E 1 0001100 Key B1 pressed

7 C 0 0000001 Key A0 released

6 F 1 0010111 Key C2 pressed

5 G 0 0001100 Key B1 released

4 A 1 0100010 Key D3 pressed

3 B 0 0010111 Key C2 released

2 H 1 0101101 Key E4 pressed

0 0101101

Key E4 released

0 I 0 0100010 Key D3 released

The MSB indicates a key press or key release in the key event register: 1 = key

press; 0 = key release.

Key Event Overflow

The ADP5587 is equipped with an overflow feature to handle

key events beyond the FIFO capacity. When all events are filled, any

additional events set the OVR_FLOW_INT bit in Register 0x02;

if the OVR_FLOW_IEN bit in Register 0x01 is set, the host

processor is also interrupted when overflow occurs. When the

FIFO is not full, new events are added as the last events.

The OVR_FLOW_M bit in Register 0x01 sets the mode of

operation during overflows. Clearing the OVR_FLOW_M bit

causes new incoming events to be discarded, and setting this bit

rolls over and overwrites old data with new data starting at the

first event.