Datasheet

ADP5585 Data Sheet
Rev. C | Page 8 of 40
DEVICE ENABLE
When sufficient voltage is applied to VDD and the
RST
pin is
driven with a logic high level, the ADP5585 starts up in standby
mode with all settings at default. The user can configure the
device via the I
2
C interface. When the
RST
pin is low, the
ADP5585 enters a reset state and all settings return to default.
The
RST
pin features a debounce filter.
If using the ADP5585ACBZ-01-R7 or ADP5585ACPZ-01-R7
device model, the
RST
pin acts as an extra row pin. Without a
reset pin, the only method to reset the device is by bringing
VDD below the UVLO threshold.
DEVICE OVERVIEW
The ADP5585 contains 10 multiconfigurable input/output pins.
Each pin can be programmed to enable the device to carry out
its various functions, as follows:
• Keypad matrix decoding (five-column by five-row matrix
maximum).
• General-purpose I/O expansion (up to 10 inputs/outputs).
• PWM generation.
• Logic function building blocks (up to three inputs and one
output).
• Two reset generators.
All 10 input/output pins have an I/O structure as shown in
Figure 6.
I/O
VDD
100kΩ
DEBOUNCE
300kΩ
300kΩ
09841-005
I/O
DRIVE
Figure 6. I/O Structure
Each I/O can be pulled up with a 100 kΩ or 300 kΩ resistor or
pulled down with a 300 kΩ resistor. For logic output drive, each
I/O has a 5 mA PMOS source and a 10 mA NMOS sink for a push-
pull type output. For open-drain output situations, the 5 mA
PMOS source is not enabled. For logic input applications, each
I/O can be sampled directly or, alternatively, sampled through a
debounce filter.
The I/O structure shown in Figure 6 allows for all GPI and GPO
functions, as well as PWM and clock divide functions. For key
matrix scan and decode, the scanning circuit uses the 100 kΩ or
300 kΩ resistor for pulling up keypad row pins and the 10 mA
NMOS sinks for grounding keypad column pins (see the Key
Scan Control section for details about key decoding).
Configuration of the device is carried out by programming an
array of internal registers via the I
2
C interface. Feedback of
device status and pending interrupts can be flagged to an
external processor by using the
INT
pin.
The ADP5585 is offered with three feature sets. Table 5 lists the
options that are available for each model of the ADP5585.
Table 5. Matrix Options by Device Model
Model Description
ADP5585ACBZ-00-R7 GPIO pull up (default option)
5-row × 5-column matrix
ADP5585ACBZ-01-R7 Row 5 added to GPIOs
6-row × 5-column matrix
ADP5585ACBZ-02-R7 No pull-up resistors to special function
pins
1
5-row × 5-column matrix
ADP5585ACBZ-04-R7 Pull-down resistors to all GPIO pins on
start-up
5-row × 5-column matrix
ADP5585ACPZ-00-R7 GPIO pull up (default option)
5-row × 5-column matrix
ADP5585ACPZ-01-R7 Row 5 added to GPIOs
6-row × 5-column matrix
ADP5585ACPZ-03-R7 Alternate I
2
C address (0x30)
5-row × 5-column matrix
1
Special function pins are defined as R0, R3, R4, and C4. See Table 4 for
details.