Datasheet

ADP5585 Data Sheet
Rev. C | Page 4 of 40
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
I
2
C TIMING SPECIFICATIONS
Delay from UVLO/Reset Inactive to I
2
C Access 60 μs
SCL Clock Frequency f
SCL
0 1000 kHz
SCL High Time t
HIGH
0.26 μs
SCL Low Time t
LOW
0.5 μs
Data Setup Time t
SU; DAT
50 ns
Data Hold Time t
HD; DAT
0 μs
Setup Time for Repeated Start t
SU; STA
0.26 μs
Hold Time for Start/Repeated Start t
HD; STA
0.26 μs
Bus Free Time for Stop and Start Condition t
BUF
0.5 μs
Setup Time for Stop Condition t
SU; STO
0.26 μs
Data Valid Time t
VD; DAT
0.45 μs
Data Valid Acknowledge t
VD; ACK
0.45 μs
Rise Time for SCL and SDA t
R
120 ns
Fall Time for SCL and SDA t
F
120 ns
Pulse Width of Suppressed Spike t
SP
0 50 ns
Capacitive Load for Each Bus Line C
B
4
550 pF
1
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Typical values are at T
A
= 25°C, VDD = 1.8 V.
2
Guaranteed by design.
3
All timers are referenced from the base oscillator and have the same ±10% accuracy.
4
C
B
is the total capacitance of one bus line in picofarads.
TIMING DIAGRAM
SDA
SCL
SDA
SCL
S
Sr PS
FIRST CLOCK CYCLE
NINTH CLOCK
NINTH CLOCK
1/
f
SCL
70%
30%
70%
30%
70%
30%
70%
30%
70%
30%
70%
30%
70%
30%
t
F
t
F
t
R
t
R
t
HIGH
t
VD; DAT
t
SU; DAT
t
SU; STA
t
HD; DAT
t
HD; STA
t
VD; ACK
t
SP
t
SU; STO
t
BUF
t
LOW
t
HD; STA
V
IL
= 0.3VDD
V
IH
= 0.7VDD
09841-002
Figure 2. I
2
C Interface Timing Diagram