Datasheet

ManualsBrandsANALOG DEVICES ManualsDev KitsPCB design board

Keypad Decoder and I/O Expansion

Data Sheet

ADP5585

Rev. C Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support www.analog.com

FEATURES

16-element FIFO for event recording

10 configurable I/Os allowing functions such as

Key pad decoding for a matrix of up to 5 × 5

11 GPIOs (5 × 6) with ADP5585ACxZ-01-R7 models

Key press/release interrupts

GPIO functions

GPI with selectable interrupt level

100 kΩ or 300 kΩ pull-up resistors

300 kΩ pull-down resistors

GPO with push-pull or open-drain

Programmable logic block

PWM generator

Internal PWM generation

External PWM with internal PWM AND function

Reset generators

C interface with fast mode plus (Fm+) support of up to 1 MHz

Open-drain interrupt output

16-ball WLCSP, 1.59 mm × 1.59 mm

16-lead LFCSP, 3 mm × 3 mm

APPLICATIONS

Keypad entries and input/output expansion capabilities

Smart phones, remote controls, and cameras

Healthcare, industrial, and instrumentation

FUNCTIONAL BLOCK DIAGRAM

SDA

GPI SCAN

AND

DECODE

UVLO

POR

C INTERFACE

OSCILLATOR

REGISTERS

KEY SCAN

AND

DECODE

LOGIC

I/O

CONFIG

INT

RST/R5

PWM

SCL

VDD

ADP5585

GND

RESET1

GEN

RESET2

GEN

09841-001

Figure 1.

GENERAL DESCRIPTION

The ADP5585 is a 10 input/output port expander with a built in

keypad matrix decoder, programmable logic, reset generator, and

PWM generator. Input/output expander ICs are used in portable

devices (phones, remote controls, and cameras) and nonportable

applications (healthcare, industrial, and instrumentation). I/O

expanders can be used to increase the number of I/Os available

to a processor or to reduce the number of I/Os required through

interface connectors for front panel designs.

The ADP5585 handles all key scanning and decoding and can

flag the main processor via an interrupt line that new key events

have occurred. GPI changes and logic changes can also be tracked

as events via the FIFO, eliminating the need to monitor different

registers for event changes. The ADP5585 is equipped with a

FIFO to store up to 16 events. Events can be read back by the

processor via an I

C-compatible interface.

The ADP5585 frees up the main processor from having to

monitor the keypad, thereby reducing power consumption

and/or increasing processor bandwidth for performing other

functions.

The programmable logic functions allow common logic require-

ments to be integrated as part of the GPIO expander, thus saving

board area and cost.

Summary of content (40 pages)

PAGE 1
Keypad Decoder and I/O Expansion ADP5585 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM VDD GND ADP5585 UVLO POR RST/R5 SDA OSCILLATOR I2C INTERFACE SCL INT KEY SCAN AND DECODE R0 R1 GPI SCAN AND DECODE R2 R3 R4 C0 C1 I/O CONFIG REGISTERS LOGIC PWM C2 C3 C4 RESET1 GEN RESET2 GEN 09841-001 16-element FIFO for event recording 10 configurable I/Os allowing functions such as Key pad decoding for a matrix of up to 5 × 5 11 GPIOs (5 × 6) with ADP5585ACxZ-01-R7 models Key press/release interrupts G
PAGE 2
ADP5585 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Functional Description .....................................................................9 Applications ....................................................................................... 1 Event FIFO .....................................................................................9 Functional Block Diagram ...........................................
PAGE 3
Data Sheet ADP5585 SPECIFICATIONS VDD = 1.8 V to 3.3 V, TA = TJ = −40°C to +85°C, unless otherwise noted 1. Table 1.
PAGE 4
ADP5585 Data Sheet Parameter I2C TIMING SPECIFICATIONS Delay from UVLO/Reset Inactive to I2C Access SCL Clock Frequency SCL High Time SCL Low Time Data Setup Time Data Hold Time Setup Time for Repeated Start Hold Time for Start/Repeated Start Bus Free Time for Stop and Start Condition Setup Time for Stop Condition Data Valid Time Data Valid Acknowledge Rise Time for SCL and SDA Fall Time for SCL and SDA Pulse Width of Suppressed Spike Capacitive Load for Each Bus Line Symbol Test Conditions/Comments Mi
PAGE 5
Data Sheet ADP5585 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VDD to GND SCL, SDA, RST, INT, R0, R1, R2, R3, R4, C0, C1, C2, C3, C4 to GND Temperature Range Operating (Ambient) Operating (Junction) Storage 1 Rating −0.3 V to +4 V −0.3 V to (VDD + 0.3 V) −40°C to +85°C1 −40°C to +125°C −65°C to +150°C In applications where high power dissipation and poor thermal resistance are present, the maximum ambient temperature may need to be derated.
PAGE 6
ADP5585 Data Sheet A SDA SCL GND R0 INT RST/R5 C0 R2 R1 C1 C2 R4 R3 C3 C4 C 13 GND R2 3 10 C4 R1 4 9 C3 TOP VIEW Not to Scale D NOTES 1. THE EXPOSED PAD IS NOT CONNECTED. IT IS RECOMMENDED TO CONNECT THE EXPOSED PAD TO GROUND FOR THERMAL DISSIPATION. 09841-003 TOP VIEW (BALL SIDE DOWN) Not to Scale 11 RST(R5) R0 5 B 12 VDD R3 2 Figure 3.
PAGE 7
Data Sheet ADP5585 THEORY OF OPERATION VDD GND ADP5585 UVLO POR RST/R5 OSCILLATOR SDA I2C INTERFACE INT SCL I2C BUSY? R0 KEY EVENT R2 (RST/R5) (C0) (C1) (C2) (C3) (C4) R3 R4 C0 (R0) (R1) (R2) (R3) (R4) (RST/R5) C1 C2 C3 C4 I/O CONFIGURATION ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 COL 0 COL 1 COL 2 COL 3 COL 4 GPIO 1 GPIO 2 GPIO 3 GPIO 4 GPIO 5 GPIO 6 (C0) (C1) (C2) (C3) (C4) GPIO 7 GPIO 8 GPIO 9 GPIO 10 GPIO 11 (R1) (R2) (R3) LA LB LC (R0) LY (C3) PWM_IN (R3) PWM_OUT (R4) RESET1
PAGE 8
ADP5585 Data Sheet DEVICE ENABLE When sufficient voltage is applied to VDD and the RST pin is driven with a logic high level, the ADP5585 starts up in standby mode with all settings at default. The user can configure the device via the I2C interface. When the RST pin is low, the ADP5585 enters a reset state and all settings return to default. The RST pin features a debounce filter. If using the ADP5585ACBZ-01-R7 or ADP5585ACPZ-01-R7 device model, the RST pin acts as an extra row pin.
PAGE 9
Data Sheet ADP5585 FUNCTIONAL DESCRIPTION EVENT FIFO EC = 3 Before going into detail on the various ADP5585 blocks, it is important to understand the function of the event FIFO. The ADP5585 features an event FIFO that can record as many as 16 events. By default, the FIFO primarily records key events, such as key press and key release. However, it is possible to configure the general-purpose input (GPI) and logic activity to generate event information on the FIFO as well.
PAGE 10
ADP5585 Data Sheet VDD low and sensing whether a row pin is low or not. All row/column pairs are scanned; therefore, if multiple keys are pressed, they are detected. KEY SCAN CONTROL C2 R0 1 2 3 4 5 6 7 8 9 R1 R2 If Switch 6 is released, the connection between R1 and C2 breaks, and R1 is pulled up high.
PAGE 11
Data Sheet ADP5585 If a smaller 2 × 2 matrix is configured, for example, by using the C2 and C3 column pins and the R1 and R2 row pins, only the four event identifiers (8, 9, 13, and 14) can possibly be observed on the FIFO, as shown in Figure 11. By default, ADP5585 records key presses and releases on the FIFO. Figure 12 illustrates what happens when a single key is pressed and released. Initially, the key scanner is idle.
PAGE 12
ADP5585 Data Sheet GPI INPUT GPI 7 Each of the 10 input/output lines can be configured as a general-purpose logic input line. Figure 15 shows a detailed representation of the GPI scan and detect block and its associated control and status signals.
PAGE 13
Data Sheet ADP5585 PWM BLOCK LOGIC BLOCK The ADP5585 features a PWM generator whose output can be configured to drive out on the R3 I/O pin. PWM on/off times are programmed via four 8-bit registers (see Figure 20). Each bit of the on or off time represents 1 µs. The highest frequency obtainable from the PWM is performed by setting the least significant bit of both the on and off time bit patterns, resulting in a 500 kHz signal with a 50% duty cycle.
PAGE 14
ADP5585 Data Sheet RESET BLOCKS ADP5585 features two reset blocks that can generate reset conditions if certain events are detected simultaneously. Up to three reset trigger events can be programmed for RESET1. Up to two reset trigger events can be programmed for RESET2. The event scan control blocks monitor whether these events are present for the duration of RESET_TRIG_TIME[2:0] (Register 0x2E, Bits[4:2]). If they are, reset-initiate signals are sent to the reset generator blocks.
PAGE 15
Data Sheet ADP5585 REGISTER INTERFACE Register access to the ADP5585 is acquired via its I2C-compatible serial interface. The interface can support clock frequencies of up to 1 MHz. If the user is accessing the FIFO or key event counter (KEC), FIFO/KEC updates are paused. If the clock frequency is very low, events may not be recorded in a timely manner. FIFO or KEC updates can happen up to 23 μs after an interrupt is asserted because of the number of I2C cycles required to perform an I2C read or write.
PAGE 16
ADP5585 Data Sheet ADP5585ACPZ-03-R7, 0x30 for the ADP5585ACPZ-03-R7 only), followed by the R/W bit set to 1 for a read cycle. The ADP5585 acknowledges the address byte by pulling the data line low. The 8-bit data is then read. The address pointer is then incremented to read the next data byte, and the host continues to pull the data line low for each byte (master acknowledge) until the n data byte is read.
PAGE 17
Data Sheet ADP5585 REGISTER MAP Table 6.
PAGE 18
ADP5585 Reg Add 0x26 Data Sheet 0x29 Reg Name GPO_OUT_ MODE_B GPIO_ DIRECTION_A GPIO_ DIRECTION_B RESET1_EVENT_A 0x2A RESET1_EVENT_B R/W 0x2B RESET1_EVENT_C R/W 0x2C RESET2_EVENT_A R/W 0x2D RESET2_EVENT_B R/W 0x2E RESET2_CFG R/W 0x2F 0x30 0x31 0x32 0x33 PWM_OFFT_LOW PWM_OFFT_HIGH PWM_ONT_LOW PWM_ONT_HIGH PWM_CFG R/W R/W R/W R/W R/W 0x34 0x35 0x36 R/W R/W R/W 0x37 0x38 0x39 0x3A LOGIC_CFG LOGIC_FF_CFG LOGIC_INT_ EVENT_EN POLL_TIME_CFG PIN_CONFIG_A PIN_CONFIG_B PIN_CONFIG_C R/W R/W R
PAGE 19
Data Sheet ADP5585 DETAILED REGISTER DESCRIPTIONS Note that N/A throughout this section means not applicable. Note: All register default to 0000 0000 unless otherwise specified. ID Register 0x00 Table 7. ID Bit Descriptions Bit(s) 7 to 4 3 to 0 Bit Name MAN_ID REV_ID Access Read only Read only Description Manufacturer ID, default = 0010 Rev ID INT_STATUS Register 0x01 Table 8.
PAGE 20
ADP5585 Data Sheet Table 11. Event Decoding Event No.
PAGE 21
Data Sheet ADP5585 FIFO_5 Register 0x07 Table 15. FIFO_5 Bit Descriptions Bit(s) 7 6 to 0 Bit Name EVENT5_STATE EVENT5_IDENTIFIER[6:0] Access Read only Read only Description Refer to Table 10. Refer to Table 10. Access Read only Read only Description Refer to Table 10. Refer to Table 10. Access Read only Read only Description Refer to Table 10. Refer to Table 10. Access Read only Read only Description Refer to Table 10. Refer to Table 10.
PAGE 22
ADP5585 Data Sheet FIFO_13 Register 0x0F Table 23. FIFO_13 Bit Descriptions Bit(s) 7 6 to 0 Bit Name EVENT13_STATE EVENT13_IDENTIFIER[6:0] Access Read only Read only Description Refer to Table 10. Refer to Table 10. Access Read only Read only Description Refer to Table 10. Refer to Table 10. Access Read only Read only Description Refer to Table 10. Refer to Table 10. Access Read only Read only Description Refer to Table 10. Refer to Table 10. FIFO_14 Register 0x10 Table 24.
PAGE 23
Data Sheet ADP5585 Bit(s) 2 Bit Name GPI_9_INT Access Read only 1 GPI_8_INT Read only 0 GPI_7_INT Read only Description 0 = no interrupt. 1 = interrupt due to GPI_9 (C2 pin). Cleared on read. 0 = no interrupt. 1 = interrupt due to GPI_8 (C1 pin). Cleared on read. 0 = no interrupt. 1 = interrupt due to GPI_7 (C0 pin). Cleared on read. GPI_STATUS_A Register 0x15 Table 29.
PAGE 24
ADP5585 Data Sheet RPULL_CONFIG_A Register 0x17 Table 31. RPULL_CONFIG_A Bit Descriptions Bit(s) 7 to 6 Bit Name R3_PULL_CFG Access Read/write Description 00 = enable 300 kΩ pull-up resistor. 01 = enable 300 kΩ pull-down resistor. 10 = enable 100 kΩ pull-up resistor. 11 = disable all pull-up/pull-down resistors. 5 to 4 R2_PULL_CFG Read/write 00 = enable 300 kΩ pull-up resistor. 01 = enable 300 kΩ pull-down resistor. 10 = enable 100 kΩ pull-up resistor. 11 = disable all pull-up/pull-down resistors.
PAGE 25
Data Sheet ADP5585 RPULL_CONFIG_C Register 0x19 Table 33. RPULL_CONFIG_C Bit Descriptions Bit(s) 7 to 6 Bit Name C3_PULL_CFG Access Read/write Description 00 = enable 300 kΩ pull-up resistor. 01 = enable 300 kΩ pull-down resistor. 10 = enable 100 kΩ pull-up resistor. 11 = disable all pull-up/pull-down resistors. 5 to 4 C2_PULL_CFG Read/write 00 = enable 300 kΩ pull-up resistor. 01 = enable 300 kΩ pull-down resistor. 10 = enable 100 kΩ pull-up resistor. 11 = disable all pull-up/pull-down resistors.
PAGE 26
ADP5585 Data Sheet GPI_INT_LEVEL_B Register 0x1C Table 36. Register 0x1C, GPI_INT_LEVEL_B Bit Descriptions Bit(s) 7 to 5 4 Bit Name N/A GPI_11_INT_LEVEL Access 3 GPI_10_INT_LEVEL Read/write 2 GPI_9_INT_LEVEL Read/write 1 GPI_8_INT_LEVEL Read/write 0 GPI_7_INT_LEVEL Read/write Read/write Description Reserved. 0 = GPI_11 interrupt is active low (GPI_11_INT sets whenever R10 is low). 1 = GPI_11 interrupt is active high (GPI_11_INT sets whenever R10 is high).
PAGE 27
Data Sheet ADP5585 GPI_EVENT_INTERRUPT_EN_A Register 0x1F Table 39. GPI_INTERRUPT_EN_A Bit Descriptions Bit(s) 7 to 6 5 Bit Name N/A GPI_6_INT_EN Access 4 GPI_5_INT_EN Read/write 3 GPI_4_INT_EN Read/write 2 GPI_3_INT_EN Read/write 1 GPI_2_INT_EN Read/write 0 GPI_1_INT_EN Read/write Read/write Description Reserved. (Reserved except for ADP5585AC_Z-01-R7 options) 0 = GPI_6_INT is disabled. 1 = GPI_6_INT enabled.
PAGE 28
ADP5585 Data Sheet DEBOUNCE_DIS_A Register 0x21 Table 41. DEBOUNCE_DIS_A Bit Descriptions Bit(s) 7 to 6 5 Bit Name N/A GPI_6_DEB_DIS Access 4 GPI_5_DEB_DIS Read/write 3 GPI_4_DEB_DIS Read/write 2 GPI_3_DEB_DIS Read/write 1 GPI_2_DEB_DIS Read/write 0 GPI_1_DEB_DIS Read/write Read/write Description Reserved. (Reserved except for ADP5585AC_Z-01-R7 options) 0 = debounce enabled on GPI 6. 1 = debounce disabled on GPI 6. 0 = debounce enabled on GPI 5. 1 = debounce disabled on GPI 5.
PAGE 29
Data Sheet ADP5585 GPO_DATA_OUT_B Register 0x24 Table 44. GPO_DATA_OUT_B Bit Descriptions Bit(s) 7 to 5 4 Bit Name N/A GPO_11_DATA Access 3 GPO_10_DATA Read/write 2 GPO_9_DATA Read/write 1 GPO_8_DATA Read/write 0 GPO_7_DATA Read/write Read/write Description Reserved. 0 = sets output low. 1 = sets output high. 0 = sets output low. 1 = sets output high. 0 = sets output low. 1 = sets output high. 0 = sets output low. 1 = sets output high. 0 = sets output low. 1 = sets output high.
PAGE 30
ADP5585 Data Sheet GPIO_DIRECTION_A Register 0x27 Table 47. GPIO_DIRECTION_A Bit Descriptions Bit(s) 7 to 6 5 Bit Name N/A GPIO_6_DIR Access 4 GPIO_5_DIR Read/write 3 GPIO_4_DIR Read/write 2 GPIO_3_DIR Read/write 1 GPIO_2_DIR Read/write 0 GPIO_1_DIR Read/write Read/write Description Reserved. (Reserved except for ADP5585AC_Z-01-R7 options) 0 = GPIO 6 is an input. 1 = GPIO 6 is an output. 0 = GPIO 5 is an input. 1 = GPIO 5 is an output. 0 = GPIO 4 is an input. 1 = GPIO 4 is an output.
PAGE 31
Data Sheet ADP5585 RESET1_EVENT_B Register 0x2A Table 50. RESET1_EVENT_B Bit Descriptions Bit(s) 7 Bit Name RESET1_EVENT_B_LEVEL Access Read/write 6 to 0 RESET1_EVENT_B[6:0] Read/write Description Defines which level the second reset event should be to generate the RESET1 signal. Refer to Table 49. Defines an event that can be used to generate the RESET1 signal. Refer to Table 11. RESET1_EVENT_C Register 0x2B Table 51.
PAGE 32
ADP5585 Data Sheet Bit(s) 4 to 2 Bit Name RESET_TRIG_TIME[2:0] Access Read/write 1 to 0 RESET_PULSE_WIDTH[1:0] Read/write Description Defines the length of time that the reset events must be active before a reset signal is generated. All events must be active at the same time for the same duration. RESET_TRIG_TIME[2:0] is common to both RESET1 and RESET2. 000 = immediate. 001 = 1.0 sec. 010 = 1.5 sec. 011 = 2.0 sec. 100 = 2.5 sec. 101 = 3.0 sec. 110 = 3.5 sec. 111 = 4.0 sec.
PAGE 33
Data Sheet ADP5585 LOGIC_CFG Register 0x34 Table 60. LOGIC_CFG Bit Descriptions Bit(s) 7 6 Bit Name N/A LY_INV Access 5 LC_INV Read/write 4 LB_INV R/W 3 LA_INV R/W 2 to 0 LOGIC_SEL[2:0] R/W Read/write Description Reserved. 0 = LY output not inverted before passing into logic block. 1 = inverts output LY from the logic block. 0 = LC input not inverted before passing into the logic block. 1 = inverts input LC before passing it into the logic block.
PAGE 34
ADP5585 Data Sheet POLL_TIME_CFG Register 0x37 Table 63. Register 0x37, POLL_TIME_CFG Bit Descriptions Bit(s) 7 to 2 1 to 0 Bit Name N/A KEY_POLL_TIME[1:0] Access Read/write Description Reserved. Configure time between consecutive scan cycles. 00 = 10 ms. 01 = 20 ms. 10 = 30 ms. 11 = 40 ms. PIN_CONFIG_A Register 0x38 Table 64.
PAGE 35
Data Sheet ADP5585 Bit(s) 5 Bit Name R4_ EXTEND_CFG Access Read/write 4 3 to 2 N/A R3_EXTEND_CFG[1:0] Read/write 1 0 N/A R0_ EXTEND_CFG Read/write Description 0 = R4 remains configured as GPIO 5. 1 = R4 reconfigured as RESET1 output. Reserved. 00 = R3 remains configured as GPIO 4. 01 = R3 reconfigured as LC input for the logic block. 10 = R3 reconfigured as PWM_OUT output from PWM block. 11 = unused. Reserved. 0 = R0 remains configured as GPIO 1.
PAGE 36
ADP5585 Data Sheet APPLICATIONS DIAGRAM VDD INT RST HOST PROCESSOR SCL SDA VDD KP/LOGIC1 OUTPUT/GPI/GPO KP/LOGIC1 INPUT/GPI/GPO SDA KP/LOGIC1 INPUT/GPI/GPO SCL RST VDD ADP5585 KP/LOGIC1 INPUT/GPI/GPO/PWM/CLK KP/RESET1 OUTPUT/GPI/GPO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 I2C INTERFACE UVLO POR OSCILLATOR R0 R1 KEY SCAN AND DECODE R2 R3 INT R4 GPI SCAN AND DECODE C4 C3 C2 I/O CONFIG C1 LOGIC PWM C0 REGISTERS RESET1 GEN GND Figure 27.
PAGE 37
Data Sheet ADP5585 OUTLINE DIMENSIONS 1.630 1.590 SQ 1.550 3 4 2 1 A BALL A1 IDENTIFIER B 1.20 REF C D 0.40 REF SEATING PLANE BOTTOM VIEW (BALL SIDE UP) SIDE VIEW COPLANARITY 0.05 0.300 0.260 0.220 0.230 0.200 0.170 10-23-2012-A 0.545 0.500 0.455 TOP VIEW (BALL SIDE DOWN) Figure 28. 16-Ball Wafer Level Chip Scale Package [WLCSP] (CB-16-10) Dimensions shown in millimeters 0.30 0.23 0.18 0.50 BSC 13 PIN 1 INDICATOR 16 1 12 EXPOSED PAD 1.75 1.60 SQ 1.45 9 TOP VIEW 0.80 0.75 0.
PAGE 38
ADP5585 Data Sheet ORDERING GUIDE Model 1 ADP5585ACBZ-00-R7 ADP5585ACBZ-01-R7 ADP5585ACBZ-02-R7 ADP5585ACBZ-04-R7 ADP5585ACPZ-00-R7 ADP5585ACPZ-01-R7 ADP5585ACPZ-03-R7 ADP5585CP-EVALZ 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 16-Ball Wafer Level Chip Scale Package [WLCSP] 16-Ball Wafer Level Chip Scale Package [WLCSP] 16-Ball Wafer Level Chip Scale Package [WLCSP] 16-Ball Wafer Level Chip Scale Package
PAGE 39
Data Sheet ADP5585 NOTES Rev.
PAGE 40
ADP5585 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2011–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09841-0-1/13(C) Rev.