Datasheet

ADP5520
Rev. A | Page 4 of 40
I
2
C TIMING SPECIFICATIONS
Table 2.
Parameter Description Min Max Unit
Delay from Reset Deassertion to I
2
C Access 60 s
f
SCL
SCL clock frequency 400 kHz
t
HIGH
SCL high time 0.6 s
t
LOW
SCL low time 1.3 s
t
SU, DAT
Data setup time 100 ns
t
HD, DAT
Data hold time 0 0.9 s
t
SU, STA
Setup time for repeated start 0.6 s
t
HD, STA
Hold time for start/repeated start 0.6 s
t
BUF
Bus free time for stop and start condition 1.3 s
t
SU, STO
Setup time for stop condition 0.6 s
t
R
Rise time for SCL and SDA 20 + 0.1 C
B
300 ns
t
F
Fall time for SCL and SDA 20 + 0.1 C
B
300 ns
t
SP
Pulse width of suppressed spike 0 50 s
C
B
1
Capacitive load for each bus line 400 pF
1
C
B
is the total capacitance of one bus line in picofarads.
SDA
SCL
S
S = START CONDITION
Sr = REPEATED START CONDITION
P = STOP CONDITION
Sr P S
t
LOW
t
R
t
HD, DAT
t
HIGH
t
SU, DAT
t
F
t
F
t
SU, STA
t
HD, STA
t
SP
t
SU, STO
t
BUF
t
R
07445-002
Figure 2. I
2
C Interface Timing Diagram