Datasheet

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ADP5520

Rev. A | Page 29 of 40

Table 33. Register 0x19, GPIO Input Status (GPIO_IN)

Bit Mnemonic R/W Description

7 D7_IN R 0 = D7 input is low.

1 = D7 input is high.

6 D6_IN R 0 = D6 input is low.

1 = D6 input is high.

5 D5_IN R 0 = D5 input is low.

1 = D5 input is high.

4 D4_IN R 0 = D4 input is low.

1 = D4 input is high.

3 D3_IN R 0 = D3 input is low.

1 = D3 input is high.

2 D2_IN R 0 = D2 input is low.

1 = D2 input is high.

1 D1_IN R 0 = D1 input is low.

1 = D1 input is high.

0 D0_IN R 0 = D0 input is low.

1 = D0 input is high.

Table 34. Register 0x1A, GPIO Output Drive (GPIO_OUT)

Bit Mnemonic R/W Description

7 D7_OUT R/W 0 = D7 output is driven low.

1 = D7 output is driven high.

6 D6_OUT R/W 0 = D6 output is driven low.

1 = D6 output is driven high.

5 D5_OUT R/W 0 = D5 output is driven low.

1 = D5 output is driven high.

4 D4_OUT R/W 0 = D4 output is driven low.

1 = D4 output is driven high.

3 D3_OUT R/W 0 = D3 output is driven low.

1 = D3 output is driven high.

2 D2_OUT R/W 0 = D2 output is driven low.

1 = D2 output is driven high.

1 D1_OUT R/W 0 = D1 output is driven low.

1 = D1 output is driven high.

0 D0_OUT R/W 0 = D0 output is driven low.

1 = D0 output is driven high.

Table 35. Register 0x1B, GPIO Interrupt Enable (GPIO_INT_EN)

Bit Mnemonic R/W Description

7 D7_IN_IEN R/W 0 = prevents D7 input from generating interrupts on nINT.

1 = allows D7 input to generate interrupts on nINT.

6 D6_IN_IEN R/W 0 = prevents D6 input from generating interrupts on nINT.

1 = allows D6 input to generate interrupts on nINT.

5 D5_IN_IEN R/W 0 = prevents D5 input from generating interrupts on nINT.

1 = allows D5 input to generate interrupts on nINT.

4 D4_IN_IEN R/W 0 = prevents D4 input from generating interrupts on nINT.

1 = allows D4 input to generate interrupts on nINT.

3 D3_IN_IEN R/W 0 = prevents D3 input from generating interrupts on nINT.

1 = allows D3 input to generate interrupts on nINT.

2 D2_IN_IEN R/W 0 = prevents D2 input from generating interrupts on nINT.

1 = allows D2 input to generate interrupts on nINT.