Datasheet

ADP5520
Rev. A | Page 16 of 40
To configure the device for key scanning and decoding, the R0,
R1, R2, and R3 pull-ups must be enabled in Register 0x1F. Key
scanning and decoding is then enabled by programming the
row and column bits in Register 0x17. The row pull-ups must
be enabled before enabling key scanning.
Figure 35 shows the row and column pins connected to a typical
4 × 4, 16-switch keypad matrix. When key scanning is idle, the
row pins are pulled high and the column pins are pulled low.
The key scanner operates by checking if the row pins are low. If
the A button in the matrix is pressed, the switch connects R0 to
C0. The key scan circuit senses that the R0 pin has been pulled low
and begins a key scan cycle. To prevent glitches or narrow press
times registering as valid key presses, the key scanner requires
the key to be pressed for two scan cycles. The key scanner has a
sampling period of 25 ms, so the key must be pressed and held
for at least 25 ms to register as being pressed. If the key is conti-
nuously pressed, the key scanner continues to sample every 25 ms.
KEYPAD
SCAN
AND
DECODE
4 × 4 KEYPAD MATRIX
C0 C1 C2 C3 R0 R1 R2 R3
VDDIO
D0_PULL D1_PULL D2_PULL D3_PULL
07445-026
A
E
I
M
B
F
J
N
C
G
K
O
D
H
L
P
Figure 35. Keypad Decode Configuration
07445-056
TIME (10ms/DIV)
2
3
CH1 2.0V
CH3 2.0V
CH2 2.0V
1
R0
C0
nINT
Figure 36. Key Press(R0,C0)
If the A button is released, the switch opens the connection
between R0 and C0, and R0 is pulled up high. The key scanner
requires that the key be released for two scan cycles. Because the
release of a key is not necessarily in sync with the key scanning
sampling period, it may take between 25 ms and 50 ms for a key
to register as being released. Once the key is registered as being
released, the key scanner returns to idle mode.
07445-057
TIME (10ms/DIV)
2
3
CH1 2.0V
CH3 2.0V
CH2 2.0V
1
R0
C0
nINT
Figure 37. Key Press (R0, C0)
Key press/release status and interrupt information is recorded
in Register 0x20 through Register 0x25. When a key is pressed,
an interrupt is generated and stored. Key press interrupts for A
through H are stored in Register 0x20, and key press interrupts for
I through P are stored in Register 0x21. The master KP_INT flag is
set if any interrupt bits are set in Register 0x20 or Register 0x21.
The nINT pin is asserted if KP_INT is set and if KP_IEN is
enabled in Register 0x01.
To deassert the nINT pin and clear the KP_INT flag, Register 0x20
and Register 0x21 must be cleared by reading them once, and
then a 1 must be written to the KP_INT bit in Register 0x00.
Figure 38 shows the interrupt generation scheme, where
KP_x_ISTAT represents any one of the 16 key press interrupt
status bits.
AND
KP_x_ISTAT KP_INT
KP_IEN
nINT
DRIVE
READ ONCE
TO CLEAR
REG 0x00
WRITE 1
TO CLEAR
REGISTERS
0x20 AND 0x21
REG 0x01
07445-027
Figure 38. Key Press Interrupt Generation
It is possible to clear key press interrupts (KP_INT = 1) and
deassert nINT while a key is still pressed.
When a key is released, an interrupt is also generated and
stored. Key release interrupts for A through H are stored in
Register 0x22, and key release interrupts for I through P are
stored in Register 0x23. The master KR_INT flag is set if any
interrupt bits are set in Register 0x22 or Register 0x23. The
nINT pin is asserted if KR_INT is set and if KR_IEN is enabled
in Register 0x01.