Datasheet

ADP5065 Data Sheet
Rev. D | Page 6 of 40
I
2
C-COMPATIBLE INTERFACE TIMING SPECIFICATIONS
Table 3.
Parameter
1
Symbol Min Typ Max Unit
I
2
C-COMPATIBLE INTERFACE
2
Capacitive Load, Each Bus Line C
S
400 pF
SCL Clock Frequency f
SCL
400 kHz
SCL High Time t
HIGH
0.6 µs
SCL Low Time t
LOW
1.3 µs
Data Setup Time t
SUDAT
100 ns
Data Hold Time t
HDDAT
0 0.9 µs
Setup Time for Repeated Start t
SUSTA
0.6 µs
Hold Time for Start/Repeated Start t
HDSTA
0.6 µs
Bus Free Time Between a Stop and a Start Condition t
BUF
1.3 µs
Setup Time for Stop Condition t
SUSTO
0.6 µs
Rise Time of SCL/SDA t
R
20 300 ns
Fall Time of SCL/SDA t
F
20 300 ns
Pulse Width of Suppressed Spike t
SP
0 50 ns
1
Guaranteed by design.
2
A master device must provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL. See Figure 2, the I
2
C timing
diagram.
Timing Diagram
S = START CONDITION
Sr = REPEATED START CONDITION
P = STOP CONDITION
t
LOW
t
SU,DAT
t
R
t
HD,DAT
t
SU,STA
t
SU,STO
t
SP
t
R
t
BUF
t
HIGH
S Sr P S
SDA
SCL
t
F
t
HD,STA
t
F
09370-002
Figure 2. I
2
C Timing Diagram