Datasheet
ADP5062 Data Sheet
Rev. B | Page 6 of 44
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
LOGIC INPUT PINS
Maximum Voltage on Digital Inputs V
DIN_MAX
5.5 V Applies to SCL, SDA, DIG_IO1, DIG_IO2, DIG_IO3
Maximum Logic Low Input Voltage V
IL
0.5 V Applies to SCL, SDA, DIG_IO1, DIG_IO2, DIG_IO3
Minimum Logic High Input Voltage V
IH
1.2 V Applies to SCL, SDA, DIG_IO1, DIG_IO2, DIG_IO3
Pull-Down Resistance
215
350
610
kΩ
Applies to DIG_IO1, DIG_IO2, DIG_IO3
1
Undervoltage lockout generated normally from ISO_Sx or ISO_Bx; in certain transition cases, it can be generated from VINx.
2
These values are programmable via I
2
C. Values are given with default register values.
3
The output current during charging may be limited by the input current limit or by the isothermal charging mode.
4
During weak charging mode, the charger provides at least 20 mA of charging current via the trickle charge branch to the battery unless trickle charging is disabled.
Any residual current that is not required by the system is also used to charge the battery.
5
Either JEITA1 (default) or JEITA2 can be selected in I
2
C, or both JEITA functions can be enabled or disabled in I
2
C.
RECOMMENDED INPUT AND OUTPUT CAPACITANCES
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
CAPACITANCES
VINx C
VINx
4 10 μF Effective capacitance
CBP C
CBP
6 10 14 nF Effective capacitance
ISO_Sx
C
ISO_Sx
10
22
100
μF
Effective capacitance
ISO_Bx C
ISO_Bx
10 22 μF Effective capacitance
I
2
C-COMPATIBLE INTERFACE TIMING SPECIFICATIONS
Table 3.
Parameter
1
Symbol Min Typ Max Unit
I
2
C-COMPATIBLE INTERFACE
2
Capacitive Load for Each Bus Line C
S
400 pF
SCL Clock Frequency f
SCL
400 kHz
SCL High Time t
HIGH
0.6 µs
SCL Low Time t
LOW
1.3 µs
Data Setup Time t
SU, DAT
100 ns
Data Hold Time t
HD, DAT
0 0.9 µs
Setup Time for Repeated Start t
SU, STA
0.6 µs
Hold Time for Start/Repeated Start t
HD, STA
0.6 µs
Bus Free Time Between a Stop and a Start Condition t
BUF
1.3 µs
Setup Time for Stop Condition t
SU, STO
0.6 µs
Rise Time of SCL/SDA
t
R
20
300
ns
Fall Time of SCL/SDA t
F
20 300 ns
Pulse Width of Suppressed Spike t
SP
0 50 ns
1
Guaranteed by design.
2
A master device must provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL (see Figure 2).