Datasheet

ADP5061 Data Sheet
Rev. C | Page 6 of 44
RECOMMENDED INPUT AND OUTPUT CAPACITANCES
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
CAPACITANCES
VINx C
VIN
4 10 F Effective capacitance
CBP C
BP
6 10 14 nF Effective capacitance
ISO_Sx C
ISO_S
20 47 100 F Effective capacitance
ISO_Bx C
ISO_B
10 22 F Effective capacitance
I
2
C-COMPATIBLE INTERFACE TIMING SPECIFICATIONS
Table 3.
Parameter
1
Symbol Min Typ Max Unit Test Conditions/Comments
I
2
C-COMPATIBLE INTERFACE
2
Capacitive Load for Each Bus Line C
S
400 pF
SCL Clock Frequency f
SCL
400 kHz
SCL High Time t
HIGH
0.6 µs
SCL Low Time t
LOW
1.3 µs
Data Setup Time t
SU, DAT
100 ns
Data Hold Time t
HD, DAT
0 0.9 µs
Setup Time for Repeated Start t
SU, STA
0.6 µs
Hold Time for Start/Repeated Start t
HD, STA
0.6 µs
Bus Free Time Between a Stop and a Start Condition t
BUF
1.3 µs
Setup Time for Stop Condition t
SU, STO
0.6 µs
Rise Time of SCL/SDA t
R
20 300 ns
Fall Time of SCL/SDA t
F
20 300 ns
Pulse Width of Suppressed Spike t
SP
0 50 ns
1
Guaranteed by design.
2
A master device must provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL (see Figure 2).
Timing Diagram
Figure 2. I
2
C Timing Diagram
SDA
S = START CONDITION
Sr = REPEATED START CONDITION
P = STOP CONDITION
SCL
S Sr P S
t
LOW
t
SU, DAT
t
HD, STA
t
SU, STO
t
HD, DAT
t
SU, STA
t
HIGH
t
R
t
F
t
R
t
F
t
SP
t
BUF
10544-002