Datasheet

ADP5061 Data Sheet
Rev. C | Page 40 of 44
I
2
C REGISTER DEFAULTS
Table 47. I
2
C Register Default Settings
Bit Name I
2
C Register Address, Bit Location Option Selection
CHG_VLIM
Address 0x03, Bits[D1:D0]
0 = limit 3.2 V, 1 = limit 3.7 V
0 = limit 3.2 V
DIS_RCH Address 0x05, Bit D7 0 = recharge enabled, 1 = recharge disabled 0 = recharge
enabled
EN_WD Address 0x06, Bit D2 0 = watchdog disabled, 1 = watchdog enabled 0 = disabled
DIS_IC1 Address 0x07, Bit D6 0 = not activated, 1 = activated 0 = not activated
EN_CHG Address 0x07, Bit D0 0 = charging disabled, 1 = charging enabled 0 = charging
disabled
EN_JEITA Address 0x08, Bit D7 0 = JEITA disabled, 1 = JEITA enabled 0 = JEITA disabled
JEITA_SELECT Address 0x08, Bit D6 0 = JEITA1 charging, 1= JEITA2 charging 0 = JEITA1
charging
EN_CHG_VLIM Address 0x08, Bit D5 0 = limit disabled, 1 = limit enabled 0 = limit disabled
IDEAL_DIODE[1:0] Address 0x08, Bits[D4:D3] 00 = ideal diode operates when V
ISO_S
< V
ISO_B
00
01 = ideal diode operates when V
ISO_S
< V
ISO_B
and
V
BAT _SNS
> V
WEAK
10 = ideal diode is disabled
11 = ideal diode is disabled
DIGITAL INPUT AND OUTPUT OPTIONS
Table 48. I
2
C Address 0x11, Bits[D1:D0] SYS_EN Output Default
Option Selection
00 = SYS_EN is activated when LDO is active and system voltage is available 00
01 = SYS_EN is activated by ISO_Bx voltage; battery charging mode
10 = SYS_EN is activated and isolation FET is disabled when battery drops below VWEAK
1
11 = SYS_EN is active in LDO mode when charger is disabled. SYS_EN is active in charging mode when VISO_B ≥ VWEAK
1
This option is active when VINx = 0 V and battery monitor is activated from Register 0x07, Bit D5 (EN_BMON).