Datasheet

Data Sheet ADP5061
Rev. C | Page 35 of 44
APPLICATIONS INFORMATION
EXTERNAL COMPONENTS
ISO_Sx (V
OUT
) Capacitor Selection
To obtain stable operation of the ADP5061 in a safe way, the
combined effective capacitance of the ISO_Sx capacitor and the
system capacitance must not be less than 20 µF and must not
exceed 100 µF at any point during operation.
When choosing the capacitor value, it is also important to
account for the loss of capacitance due to the output voltage
dc bias. Ceramic capacitors are manufactured with a variety of
dielectrics, each with a different behavior over temperature and
applied voltage. Capacitors must have a dielectric that is adequate
to ensure the minimum capacitance over the necessary
temperature range and dc bias conditions. X5R or X7R dielectrics
with a voltage rating of 6.3 V or higher are recommended for best
performance. Y5V and Z5U dielectrics are not recommended
for use with any dc-to-dc converter because of their poor
temperature and dc bias characteristics.
The worst-case capacitance accounting for capacitor variation
over temperature, component tolerance, and voltage is calcu-
lated using the following equation:
C
EFF
= C
OUT
× (1 − TEMPCO) × (1 − TOL)
where:
C
EFF
is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient
(TEMPCO) over the −40°C to +85°C temperature range is
assumed to be 15% for an X7R dielectric. The tolerance of the
capacitor (TOL) is assumed to be 20%, and C
OUT
is 30.4 μF at
5.0 V, as shown in Figure 38.
Figure 38. Murata GRM32ER61A476ME20C Capacitance vs. Bias Voltage
Substituting these values in the equation yields
C
EFF
= 34.3 μF × (1 − 0.15) × (1 − 0.2) ≈ 20.7 μF
To guarantee the performance of the charger in various operation
modes including trickle charge, constant current charge, and
constant voltage charge, it is imperative that the effects of dc
bias, temperature, and tolerances on the behavior of the capaci-
tors be evaluated for each application.
Splitting ISO_Sx Capacitance
In many applications, the total ISO_Sx capacitance consists of a
number of capacitors. The system voltage node (ISO_Sx) usually
supplies a single regulator or a number of ICs and regulators,
each of which requires a capacitor close to its power supply
input (see Figure 39).
The capacitance close to the ADP5061 ISO_Sx output should be
at least 10 µF, as long as the total effective capacitance is at least
20 µF at any point during operation.
Figure 39. Splitting ISO_Sx Capacitance
ISO_Bx Capacitor Selection
The ISO_Bx effective capacitance (including temperature and
dc bias effects) must not be less than 10 µF at any point during
operation. Typically, a nominal capacitance of 22 µF is required
to fulfill the condition at all points of operation. Suggestions for
an ISO_Bx capacitor are listed in Table 35.
CBP Capacitor Selection
The internal supply voltage of the ADP5061 is equipped with a
noise suppressing capacitor at the CBP terminal. Do not allow CBP
capacitance to exceed 14 nF at any point during operation. Do
not connect any external voltage source, any resistive load, or
any other current load to the CBP terminal. Suggestions for a
CBP capacitor are listed in Table 36.
20
25
30
35
40
45
50
55
60
0 1 2 3 4 5
CAPACITANCE (µF)
DC BIAS VOLTAGE (V)
10544-041
ADP5061
IC1
IC2
ISO_Sx
VIN1
VIN2
C
IN1
C
IN2
C
ISO_S
≥10µF
C
ISO_B
≥10µF
SUM OF EFFECTIVE
CAPACITANCES
ON ISO_Sx NODE ≥ 20µF
+
ISO_Bx
10544-038