Datasheet

ADP5052 Data Sheet
Rev. 0 | Page 34 of 40
VREG
CHANNEL 2
BUCK REGULATOR
(1.2A/2.5A/4A)
CHANNEL 3
BUCK REGULATOR
(1.2A)
OSCILLATOR
INT VREG
100mA
Q1
Q2
L1
1.5µH
1.5µH
6.8µH
10µH
L2
5V REG
SYNC/MODE
RT
FB1
BST1
SW1
DL1
PGND
DL2
SW2
BST2
FB2
VREG
L3
BST3
SW3
FB3
PGND3
L4
BST4
SW4
FB4
PGND4
VREG
PVIN1
COMP1
EN1
PVIN2
COMP2
EN2
PVIN3
SS34
COMP3
EN3
PVIN4
COMP4
EN4
C2
10µF
2.7nF
10kΩ
100kΩ
600kΩ
31.6kΩ
2.7nF
6.81kΩ
2.7nF
6.81kΩ
C1
1.0µF
C4
100µF
C3
0.1µF
C5
10µF
C6
0.1µF
C8
10µF
C9
0.1µF
C10
22µF
C11
10µF
C12
0.1µF
C13
22µF
C14
1µF
C15
1µF
12V
VOUT1
VOUT3
1.2V/8A
1.5V/1.2A
3.3V/1.2A
2.5V/200mA
VOUT4
22kΩ
22kΩ
5V REG
EXPOSED PAD
SS12
C0
1.0µF
VDD
CHANNEL 5
200mA LDO
REGULATOR
FB5
EN5
VOUT5
VOUT5
ADP5052
CHANNEL 1
BUCK REGULATOR
(1.2A/2.5A/4A)
CHANNEL 4
BUCK REGULATOR
(1.2A)
C16
100µF
VREG
PVIN5
4.99kΩ
10kΩ
8.87kΩ
31.6kΩ
40.2kΩ
10.2kΩ
10.2kΩ
10kΩ
Si7232DN
(16.4mΩ)
10900-165
PWRGD
Figure 56. Typical Channel 1/Channel 2 Parallel Output Application, 600 kHz Switching Frequency, Adjustable Output Model