Datasheet

Data Sheet ADP5050
Rev. 0 | Page 9 of 60
I
2
C INTERFACE TIMING SPECIFICATIONS
T
A
= 25°C, V
VDD
= 3.3 V, V
VDDIO
= 3.3 V, unless otherwise noted.
Table 4.
Parameter Min Typ Max Unit Description
f
SCL
400 kHz SCL clock frequency
t
HIGH
0.6 µs SCL high time
t
LOW
1.3 µs SCL low time
t
SU, DAT
100 ns Data setup time
t
HD,DAT
0 0.9 µs Data hold time
1
t
SU,STA
0.6 µs Setup time for a repeated start condition
t
HD,STA
0.6 µs Hold time for a start or repeated start condition
t
BUF
1.3 µs Bus free time between a stop condition and a start condition
t
SU,STO
0.6 µs Setup time for a stop condition
t
R
20 + 0.1C
B
2
300 ns Rise time of SCL and SDA
t
F
20 + 0.1C
B
2
300 ns Fall time of SCL and SDA
t
SP
0 50 ns Pulse width of suppressed spike
C
B
2
400 pF Capacitive load for each bus line
1
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH
minimum of the SCL signal) to bridge the undefined region of the
SCL falling edge.
2
C
B
is the total capacitance of one bus line in picofarads (pF).
Timing Diagram
S SP
Sr
S = START CONDITION
Sr = REPEATED START CONDITION
P = STOP CONDITION
SCL
SDA
t
HD,DAT
t
SU,DAT
t
HD,STA
t
SU,STA
t
SU,STO
t
HIGH
t
R
t
F
t
F
t
SP
t
R
t
LOW
t
BUF
10899-102
Figure 3. I
2
C Interface Timing Diagram