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ADP5050 Data Sheet
Rev. 0 | Page 52 of 60
REGISTER 14: INT_STATUS (INTERRUPT STATUS
READBACK), ADDRESS 0x0E
Register 14 contains the interrupt status for the following events:
junction temperature overheat warning, low input voltage warn-
ing, and power-good signal failure on Channel 1 to Channel 4.
When any of these unmasked events occur, the nINT pin is
pulled low to indicate a fault condition. (Masking of these events
is configured in Register 15.) To determine the cause of the fault,
read this register. Latched flags are not reset when the fault dis-
appears but are cleared only when a 1 is written to the appropriate
bit or when all ENx pins = 0.
Table 45. Register 14 Bit Assignments
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserved TEMP_INT LVIN_INT PWRG4_INT PWRG3_INT PWRG2_INT PWRG1_INT
Table 46. INT_STATUS Register, Bit Function Descriptions
Bits Bit Name Access Description
[7:6] Reserved R/W Reserved.
5 TEMP_INT Read/
self-clear
This bit indicates whether the junction temperature threshold has been exceeded.
0 = junction temperature has not exceeded the threshold.
1 = junction temperature has exceeded the threshold.
4 LVIN_INT Read/
self-clear
This bit indicates whether the low voltage input threshold has been exceeded.
0 = low voltage input has not fallen below the threshold.
1 = low voltage input has fallen below the threshold.
3 PWRG4_INT Read/
self-clear
The power-good interrupt is masked when the part is initialized and during a normal shutdown.
0 = no power-good failure has been detected on Channel 4.
1 = power-good failure has been detected on Channel 4.
2 PWRG3_INT Read/
self-clear
The power-good interrupt is masked when the part is initialized and during a normal shutdown.
0 = no power-good failure has been detected on Channel 3.
1 = power-good failure has been detected on Channel 3.
1 PWRG2_INT Read/
self-clear
The power-good interrupt is masked when the part is initialized and during a normal shutdown.
0 = no power-good failure has been detected on Channel 2.
1 = power-good failure has been detected on Channel 2.
0 PWRG1_INT Read/
self-clear
The power-good interrupt is masked when the part is initialized and during a normal shutdown.
0 = no power-good failure has been detected on Channel 1.
1 = power-good failure has been detected on Channel 1.