Datasheet

ADP5050 Data Sheet
Rev. 0 | Page 50 of 60
REGISTER 11: PWRGD_MASK (CHANNEL MASK
CONFIGURATION FOR PWRGD PIN), ADDRESS 0x0B
Register 11 is used to mask or unmask the power-good status of
Channel 1 to Channel 4; when unmasked, a power-good failure
on any of these channels triggers the PWRGD pin. The output
of the PWRGD pin represents the logical AND of all unmasked
PWRGD signals; that is, the PWRGD pin is pulled low by any
PWRGD signal failure. There is a 1 ms validation delay time
before the PWRGD pin goes high. The default value for the
power-good mask configuration can be programmed by factory
fuse (mask function enabled or disabled for all four buck
regulators).
Table 39. Register 11 Bit Assignments
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserved MASK_CH4 MASK_CH3 MASK_CH2 MASK_CH1
Table 40. PWRGD_MASK Register, Bit Function Descriptions
Bits
Bit Name
Access
Description
[7:4] Reserved R/W Reserved.
3 MASK_CH4 R/W The default value can be programmed by factory fuse.
0 = mask power-good status of Channel 4.
1 = output power-good status of Channel 4 to the PWRGD pin.
2 MASK_CH3 R/W The default value can be programmed by factory fuse.
0 = mask power-good status of Channel 3.
1 = output power-good status of Channel 3 to the PWRGD pin.
1 MASK_CH2 R/W The default value can be programmed by factory fuse.
0 = mask power-good status of Channel 2.
1 = output power-good status of Channel 2 to the PWRGD pin.
0 MASK_CH1 R/W The default value can be programmed by factory fuse.
0 = mask power-good status of Channel 1.
1 = output power-good status of Channel 1 to the PWRGD pin.