Datasheet

ADP5050 Data Sheet
Rev. 0 | Page 4 of 60
DETAILED FUNCTIONAL BLOCK DIAGRAM
Q1
Q
DG1
Q
PWRGD
Q
DG3
UVLO1
PVIN1
SW1
BST1
VREG
VREG
DRIVER
DRIVER
PGND
DL1
CONTROL LOGIC
AND MOSFET
DRIVER WITH
ANTICROSS
PROTECTION
CONTROL LOGIC
AND MOSFET
DRIVER WITH
ANTICROSS
PROTECTION
EN1
0.8V
1MΩ
HICCUP
AND
LATCH-OFF
OCP
COMP1
FB1
0.8V
CLK1
SLOPE
COMP
CLK1
0.72V
PWRGD1
ZERO
CROSS
CURRENT-LIMIT
SELECTION
FREQUENCY
FOLDBACK
+
–
+
–
+
–
–
+
+
–
+
–
+
–
CHANNEL 1 BUCK REGULATOR
DUPLICATE CHANNEL 1
CHANNEL 2 BUCK REGULATOR
CURRENT BALANCE
EN2
COMP2
FB2
DL2
PVIN2
SW2
BST2
DISCHARGE
SWITCH
VID1
0.99V
OVP
LATCH-OFF
EA1
CMP1
RT
OSCILLATOR
SYNC/MODE
SOFT START
DECODER
SS12
SS34
VDD
VREG
INTERNAL
REGULATOR
PVIN1
VDDIO
SCL
SDA
I
2
C
INTERFACE
AND
REGISTERS
VREG
POWER-ON
RESET
PWRGD
HOUSEKEEPING
LOGIC
nINT
UVLO3
PVIN3
SW3
BST3
VREG
VREG
DRIVER
Q3
Q4
DRIVER
PGND3
EN3
COMP3
FB3
CHANNEL 3 BUCK REGULATOR
DUPLICATE CHANNEL 3
CHANNEL 4 BUCK REGULATOR
EN4
COMP4
FB4
PGND4
PVIN4
SW4
BST4
A
CS1
+
–
–
+
A
CS3
Q7
PVIN5
VOUT5
EN5
LDO
CONTROL
FB5
0.5V
CHANNEL 5 LDO REGULATOR
0.8V
1MΩ
+
–
DISCHARGE
SWITCH
0.8V
1MΩ
HICCUP
AND
LATCH-OFF
OCP
0.8V
CLK3
SLOPE
COMP
CLK3
0.72V
PWRGD3
FREQUENCY
FOLDBACK
+
–
+
–
+
–
–
+
+
–
+
–
VID3
0.99V
OVP
LATCH-OFF
EA3
CMP3
ZERO
CROSS
EA5
10899-202
Figure 2.