Datasheet

ADP5050 Data Sheet
Rev. 0 | Page 38 of 60
TYPICAL APPLICATION CIRCUITS
VREG
CHANNEL 2
BUCK REGULATOR
(1.2A/2.5A/4A)
CHANNEL 3
BUCK REGULATOR
(1.2A)
OSCILLATOR
INT VREG
100mA
Q1
Q2
L1
L2
5V REG
SYNC/MODE
RT
FB1
BST1
SW1
DL1
PGND
DL2
SW2
BST2
FB2
L3
BST3
SW3
FB3
PGND3
ALERT
L4
10µH
4.7µH
4.7µH
2.2µH
SiA906EDJ
(46mΩ)
31.6kΩ
6.81kΩ
2.7nF
6.81kΩ
2.7nF
6.81kΩ
2.7nF
6.81kΩ
2.7nF
BST4
SW4
FB4
PGND4
nINT
VREG
PVIN1
COMP1
EN1
PVIN2
COMP2
EN2
PVIN3
SS34
COMP3
EN3
VDDIO
OPTIONAL
I
2
C INTERFACE
PVIN4
COMP4
EN4
SCL
SDA
C2
10µF
C1
1.0µF
C4
47µF
C3
0.1µF
C5
10µF
C6
0.1µF
C9
0.1µF
C7
47µF
C8
10µF
C10
22µF
C11
10µF
C12
0.1µF
C13
22µF
12V
VOUT1
VOUT2
VDDIO
PROCESSOR
3.3V/2.5A
2.85V/100mA
1.5V/1.2A
4.0V TO 4.5V/1.2A
(DVS)
1.1V TO 1.3V/2.5A
(DVS)
DDR
TERM. LDO
DDR
MEMORY
RFPA
RF
TRANSCEIVER
nINT
VCORE
I/O
VOUT3
VOUT4
PWRGD
5V REG
EXPOSED PAD
SS12
VREG
C0
1.0µF
VDD
CHANNEL 5
200mA LDO
REGULATOR
FB5
EN5
VOUT5
PVIN5
C15
1µF
10kΩ
47kΩ
C14
1µF
VOUT5
ADP5050
CHANNEL 1
BUCK REGULATOR
(1.2A/2.5A/4A)
CHANNEL 4
BUCK REGULATOR
(1.2A)
VREG
OPTIONAL
I
2
C
INTERFACE
SCL
SDA
SCL
SDA
10899-056
I
2
C
Figure 66. Typical Femtocell Application, 600 kHz Switching Frequency, Fixed Output Model