Datasheet

ADP5050 Data Sheet
Rev. 0 | Page 32 of 60
COMPENSATION COMPONENTS DESIGN
For the peak current-mode control architecture, the power
stage can be simplified as a voltage controlled current source
that supplies current to the output capacitor and load resistor.
The simplified loop is composed of one domain pole and a zero
contributed by the output capacitor ESR. The control-to-output
transfer function is shown in the following equations:








×π×
+








×π×
+
××
==
p
z
VI
COMP
OUT
vd
f
s
f
s
RA
sV
sV
sG
2
1
2
1
)(
)
(
)(
OUT
ESR
z
CR
f
××π×
=
2
1
( )
OUT
ESR
p
CRR
f
×+×π×
=
2
1
where:
A
VI
= 10 A/V for Channel 1 or Channel 2, and 3.33 A/V for
Channel 3 or Channel 4.
R is the load resistance.
R
ESR
is the equivalent series resistance of the output capacitor.
C
OUT
is the output capacitance.
The ADP5050 uses a transconductance amplifier as the error
amplifier to compensate the system. Figure 61 shows the sim-
plified peak current-mode control small signal circuit.
R
ESR
R
+
–
g
m
R
C
C
CP
C
OUT
C
C
R
TOP
R
BOT
–
+
A
VI
V
OUT
V
COMP
V
OUT
10899-054
Figure 61. Simplified Peak Current-Mode Control Small Signal Circuit
The compensation components, R
C
and C
C
, contribute a zero;
R
C
and the optional C
CP
contribute an optional pole.
The closed-loop transfer equation is as follows:
)(
1
1
)( sG
s
CC
CCR
s
sCR
CC
g
RR
R
sT
vd
CPC
CPCC
CC
CPC
m
TOPBOT
BOT
V
×








×
+
××
+×
××+
×
+
−
×
+
=
The following guidelines show how to select the compensation
components—R
C
, C
C
, and C
CP
—for ceramic output capacitor
applications.
1. Determine the cross frequency (f
C
). Generally, f
C
is between
f
SW
/12 and f
SW
/6.
2. Calculate R
C
using the following equation:
VI
m
C
OUTOUT
C
Ag
fCV
R
××
×××π×
=
V8.0
2
3. Place the compensation zero at the domain pole (f
P
).
Calculate C
C
using the following equation:
( )
C
OUT
ESR
C
R
CRR
C
×+
=
4. C
CP
is optional. It can be used to cancel the zero caused
by the ESR of the output capacitor. Calculate C
CP
using
the following equation:
C
OUT
ESR
CP
R
CR
C
×
=
POWER DISSIPATION
The total power dissipation in the ADP5050 simplifies to
P
D
= P
BUCK1
+ P
BUCK2
+ P
BUCK3
+ P
BUCK4
+ P
LDO
Buck Regulator Power Dissipation
The power dissipation (P
LOSS
) for each buck regulator includes
power switch conduction losses (P
COND
), switching losses (P
SW
),
and transition losses (P
TRAN
). Other sources of power dissipation
exist, but these sources are generally less significant at the high
output currents of the application thermal limit.
Use the following equation to estimate the power dissipation of
the buck regulator:
P
LOSS
= P
COND
+ P
SW
+ P
TRAN
Power Switch Conduction Loss (P
COND
)
Power switch conduction losses are caused by the flow of output
current through both the high-side and low-side power switches,
each of which has its own internal on resistance (R
DSON
).
Use the following equation to estimate the power switch
conduction loss:
P
COND
= (R
DSON_HS
× D + R
DSON_LS
× (1 − D)) × I
OUT
2
where:
R
DSON_HS
is the on resistance of the high-side MOSF ET.
R
DSON_LS
is the on resistance of the low-side MOSFET.
D is the duty cycle (D = V
OUT
/V
IN
).