Datasheet

Data Sheet ADP5050
Rev. 0 | Page 29 of 60
APPLICATIONS INFORMATION
ADIsimPower DESIGN TOOL
The ADP5050 is supported by the ADIsimPower™ design tool
set. ADIsimPower is a collection of tools that produce complete
power designs optimized for a specific design goal. The tools
enable the user to generate a full schematic and bill of materials
and to calculate performance in minutes. ADIsimPower can
optimize designs for cost, area, efficiency, and part count while
taking into consideration the operating conditions and limitations
of the IC and all real external components. The ADIsimPower
tool can be found at www.analog.com/ADIsimPower; the user
can request an unpopulated board through the tool.
PROGRAMMING THE ADJUSTABLE OUTPUT
VOLTAGE
The output voltage of the ADP5050 is externally set by a resistive
voltage divider from the output voltage to the FBx pin. To limit
the degradation of the output voltage accuracy due to feedback
bias current, ensure that the bottom resistor in the divider is not
too large—a value of less than 50 kΩ is recommended.
The equation for the output voltage setting is
V
OUT
= V
REF
× (1 + (R
TOP
/R
BOT
))
where:
V
OUT
is the output voltage.
V
REF
is the feedback reference voltage: 0.8 V for Channel 1 to
Channel 4 and 0.5 V for Channel 5.
R
TOP
is the feedback resistor from V
OUT
to FB.
R
BOT
is the feedback resistor from FB to ground.
No resistor divider is required in the fixed output options. Each
channel has VIDx bits to program the output voltage for a specific
range (see Table 9). If a different fixed output voltage (default
VID code) is required, contact your local Analog Devices sales
or distribution representative.
VOLTAGE CONVERSION LIMITATIONS
For a given input voltage, upper and lower limitations on the
output voltage exist due to the minimum on time and the
minimum off time.
The minimum output voltage for a given input voltage and
switching frequency is limited by the minimum on time. The
minimum on time for Channel 1 and Channel 2 is 117 ns
(typical); the minimum on time for Channel 3 and Channel 4
is 90 ns (typical). The minimum on time increases at higher
junction temperatures.
Note that in forced PWM mode, Channel 1 and Channel 2 can
potentially exceed the nominal output voltage when the mini-
mum on time limit is exceeded. Careful switching frequency
selection is required to avoid this problem.
The minimum output voltage in continuous conduction mode
(CCM) for a given input voltage and switching frequency can be
calculated using the following equation:
V
OUT_MIN
= V
IN
× t
MIN_ON
× f
SW
− (R
DSON1
− R
DSON2
) ×
I
OUT_MIN
× t
MIN_ON
× f
SW
− (R
DSON2
+ R
L
) × I
OUT_MIN
(1)
where:
V
OUT_MIN
is the minimum output voltage.
t
MIN_ON
is the minimum on time.
f
SW
is the switching frequency.
R
DSON1
is the on resistance of the high-side MOSFET.
R
DSON2
is the on resistance of the low-side MOSFET.
I
OUT_MIN
is the minimum output current.
R
L
is the resistance of the output inductor.
The maximum output voltage for a given input voltage and
switching frequency is limited by the minimum off time and
the maximum duty cycle. Note that the frequency foldback
feature helps to increase the effective maximum duty cycle by
lowering the switching frequency, thereby decreasing the dropout
voltage between the input and output voltages (see the Frequency
Foldback section).
The maximum output voltage for a given input voltage and switch-
ing frequency can be calculated using the following equation:
V
OUT_MAX
= V
IN
× (1 − t
MIN_OFF
× f
SW
) − (R
DSON1
− R
DSON2
) ×
I
OUT_MAX
× (1 − t
MIN_OFF
× f
SW
) − (R
DSON2
+ R
L
) × I
OUT_MAX
(2)
where:
V
OUT_MAX
is the maximum output voltage.
t
MIN_OFF
is the minimum off time.
f
SW
is the switching frequency.
R
DSON1
is the on resistance of the high-side MOSFET.
R
DSON2
is the on resistance of the low-side MOSFET.
I
OUT_MAX
is the maximum output current.
R
L
is the resistance of the output inductor.
As shown in Equation 1 and Equation 2, reducing the switching
frequency eases the minimum on time and off time limitations.
CURRENT-LIMIT SETTING
The ADP5050 has three selectable current-limit thresholds for
Channel 1 and Channel 2. Make sure that the selected current-
limit value is larger than the peak current of the inductor, I
PEAK
.
See Table 11 for the current-limit configuration for Channel 1
and Channel 2.