Datasheet

ADP5050 Data Sheet
Rev. 0 | Page 28 of 60
I
2
C INTERFACE TIMING DIAGRAMS
Figure 59 shows the timing diagram for the I
2
C write operation.
Figure 60 shows the timing diagram for the I
2
C read operation.
The subaddress is used to select one of the user registers in the
ADP5050. The ADP5050 sends data to and from the register
specified by the subaddress.
SCL
CHIP ADDRESS
SDA
A0A1A2A3A4A5A6 A0A1A2A3A4A5A6A7
0 000100
1
D0D1D2D3D4D5D6D7
SUBADDRESS
WRITE DATA
ACK BY SLAVE
WRITE
START
ACK BY SLAVE
ACK BY SLAVE
R/W
STOP
NOTES
1. MAXIMUM SCL FREQUENCY IS 400kHz.
2. NO RESPONSE TO GENERAL CALLS.
OUTPUT BY PROCESSOR
OUTPUT BY ADP5050
10899-052
Figure 59. I
2
C Write to Register
SCL
CHIP ADDRESS
SDA
A0A1A2A3A4A5A6 A0A1A2A3A4A5A6A7
0 0001001
10001001
D0D1
D2D3D4D5D6D7
SUBADDRESS
CHIP ADDRESS
READ DATA
NOTES
1. MAXIMUM SCL FREQUENCY IS 400kHz.
2. NO RESPONSE TO GENERAL CALLS.
OUTPUT BY PROCESSOR
OUTPUT BY ADP5050
ACK BY SLAVE
WRITE
START
ACK BY SLAVE
READ
ACK BY SLAVE
NO ACK BY MASTER
TO STOP READING
R/W
A0A1A2A3A4A5A6
R/W
STOP
10899-053
Figure 60. I
2
C Read from Register