Datasheet

Data Sheet ADP5050
Rev. 0 | Page 27 of 60
I
2
C INTERFACE
The ADP5050 includes an I
2
C-compatible serial interface for
control of the power management blocks and for readback of
system status (see Figure 57). The I
2
C interface operates at clock
frequencies of up to 400 kHz.
I
2
C REGISTER
SCL
SDA
LEVEL
SHIFTER
VDDIO
VDD
VDDIO
UVLO_VDDIO
TRIM DATA
SCP/OVP
VDDIO
VDD
VDD
VDD
VDDIO
10899-051
Figure 57. I
2
C Interface Block Diagram
Note that the ADP5050 does not respond to general calls. The
ADP5050 accepts multiple masters, but if the device is in read
mode, access is limited to one master until the data transmission
is completed.
The I
2
C serial interface can be used to access the internal registers
of the ADP5050. For complete information about the ADP5050
registers, see the Register Map section.
SDA AND SCL PINS
The ADP5050 has two dedicated I
2
C interface pins, SDA and
SCL. SDA is an open-drain line for receiving and transmitting
data. SCL is an input line for receiving the clock signal. Pull up
these pins to the VDDIO supply using external resistors.
Serial data is transferred on the rising edge of SCL. The read
data is generated at the SDA pin in read mode.
I
2
C ADDRESSES
The default 7-bit I
2
C chip address for the ADP5050 is 0x48
(1001000 in binary). A different I
2
C address can be configured
using the optional A0 pin, which can replace the power-good
functionality on Pin 20. (For information about obtaining an
ADP5050 model with Pin 20 functioning as the A0 pin, contact
your local Analog Devices sales or distribution representative.)
The A0 pin allows the use of two ADP5050 devices on the same
I
2
C communication bus. Figure 58 shows two ADP5050 devices
configured with different I
2
C addresses using the A0 pin.
10899-050
SCL
VDDIO
I
2
C INTERFACE
I
2
C ADDRESS = 0x48 I
2
C ADDRESS = 0x49
A0
SDA
SCL
VDDIO
A0
VREG
SDA
Figure 58. Two ADP5050 Devices Configured with Different I
2
C Addresses
(A0 Function Replaces PWRGD Function on Pin 20)
SELF-CLEAR REGISTER BITS
Register 12 and Register 14 are status registers that contain self-
clear register bits. These bit are cleared automatically when a 1
is written to the status bit. Therefore, it is not necessary to write
a 0 to the status bit to clear it.