Datasheet

ADP5050 Data Sheet
Rev. 0 | Page 26 of 60
THERMAL SHUTDOWN
If the ADP5050 junction temperature exceeds 150°C, the thermal
shutdown circuit turns off the IC except for the internal linear
regulators. Extreme junction temperatures can be the result of
high current operation, poor circuit board design, or high ambient
temperature. A 15°C hysteresis is included so that the ADP5050
does not return to operation after thermal shutdown until the
on-chip temperature falls below 135°C. When the part exits ther-
mal shutdown, a soft start is initiated for each enabled channel.
The thermal shutdown status can be read via the I
2
C interface
(Register 12, LCH_STATUS). When thermal shutdown is detected,
the TSD_LCH bit (Bit 4) is set to 1. To clear the status bit, write a
1 to the bit (provided that the fault no longer persists). The status
bit is latched until a 1 is written to the bit or the part is reset by
the internal VDD power-on reset signal.
OVERHEAT DETECTION
In addition to thermal shutdown protection, the ADP5050
provides an overheat warning function, which compares the
junction temperature with the specified overheat threshold:
105°, 115°, or 125°. The overheat threshold is configured in
Register 9, TH_CFG. Unlike thermal shutdown, the overheat
detection function sends a warning signal but does not shut
down the part. When the junction temperature exceeds the
overheat threshold, the status bit TEMP_INT in Register 14
is set to 1. The status bit is latched until a 1 is written to the bit,
all ENx pins are taken low, or the part is reset by the internal
VDD power-on reset signal.
The overheat detection function can be used to send a warning
signal to the host processor. After the host processor detects the
overheat warning signal, the processor can take action to prepare
for a possible impending thermal shutdown.
Figure 54 shows the overheat warning function.
JUNCTION TEMPERATURE
TIME
TEMP_INT
(HEAT STATUS)
OVERHEAT
CONDITION
DETECTED
NORMAL
TEMPERATURE
115°C
(ADJUSTABLE)
10899-047
Figure 54. Overheat Warning Function
LOW INPUT VOLTAGE DETECTION
In addition to undervoltage lockout (UVLO), the ADP5050
provides a low input voltage detection circuit to monitor PVIN1;
this circuit compares the input voltage with the specified voltage
threshold. The voltage threshold can be set from 4.2 V to 11.2 V
in steps of 0.5 V using Register 9, TH_CFG. Unlike UVLO shut-
down, the low input voltage detection function sends a warning
signal but does not shut down the part. When the PVIN1 input
voltage falls below the threshold, the status bit LVIN_INT in
Register 14 is set to 1. The status bit is latched until a 1 is written
to the bit, all ENx pins are taken low, or the part is reset by the
internal VDD power-on reset signal.
The low input voltage detection function can be used to send a
warning signal to the host processor. After the host processor
detects the low input voltage warning signal, the processor can
take action to prepare for a possible impending UVLO shutdown.
Figure 55 shows the low input voltage warning function.
INPUT VOLTAGE ON PVIN1
TIME
LVIN_INT
(LVIN STATUS)
LOW INPUT
VOLTAGE
CONDITION
DETECTED
12V INPUT
VOLTAGE
10.7V
(ADJUSTABLE)
10899-048
Figure 55. Low Input Voltage Warning Function (V
IN
= 12 V)
LDO REGULATOR
The ADP5050 integrates a general-purpose LDO regulator with
low quiescent current and low dropout voltage. The LDO regu-
lator provides up to 200 mA of output current.
The LDO regulator operates with an input voltage of 1.7 V to
5.5 V. The wide supply range makes the regulator suitable for
cascading configurations where the LDO supply voltage is
provided from one of the buck regulators. The LDO output
voltage is set using an external resistor divider (see Figure 56).
LDO
FB5
VOUT5
EN5
PVIN5
C1
1µF
R
A
R
B
C2
1µF
1.7V TO 5.5V
10899-049
Figure 56. 200 mA LDO Regulator
The LDO regulator provides a high power supply rejection ratio
(PSRR), low output noise, and excellent line and load transient
response using small 1 µF ceramic input and output capacitors.