Datasheet

ADP5050 Data Sheet
Rev. 0 | Page 20 of 60
ADJUSTABLE AND FIXED OUTPUT VOLTAGES
The ADP5050 provides adjustable and fixed output voltage
settings via the I
2
C interface or factory fuse. For the adjustable
output settings, use an external resistor divider to set the desired
output voltage via the feedback reference voltage (0.8 V for
Channel 1 to Channel 4, and 0.5 V for Channel 5).
For the fixed output settings, the feedback resistor divider is
built into the ADP5050, and the feedback pin (FBx) must be
tied directly to the output. Each buck regulator channel can be
programmed for a specific output voltage range using the VIDx
bits in Register 2 to Register 4. Tabl e 9 lists the fixed output
voltage ranges configured by the VIDx bits.
Table 9. Fixed Output Voltage Ranges Set by the VIDx Bits
Channel Fixed Output Voltage Range Set by the VIDx Bits
Channel 1 0.85 V to 1.6 V in 25 mV steps
Channel 2 3.3 V to 5.0 V in 300 mV or 200 mV steps
Channel 3 1.2 V to 1.8 V in 100 mV steps
Channel 4
2.5 V to 5.5 V in 100 mV steps
The output range can also be programmed by factory fuse. If
a different output voltage range is required, contact your local
Analog Devices, Inc., sales or distribution representative.
DYNAMIC VOLTAGE SCALING (DVS)
The ADP5050 provides a dynamic voltage scaling (DVS) function
for Channel 1 and Channel 4; these outputs can be programmed
in real time via the I
2
C interface (Register 5, DVS_CFG). The
DVS_CFG register is used to enable DVS and to set the step
interval during the transition (see Table 28).
It is recommended that the user enable the DVS function before
setting the output voltage for Channel 1 or Channel 4. (The out-
put voltage for Channel 1 is set using the VID1 bits in Register 2;
the output voltage for Channel 4 is set using the VID4 bits in
Register 4.) If DVS is enabled after the VID value is set, the output
voltage changes rapidly to the next target voltage, which can
result in problems such as a PWRGD failure or OVP and OCP
events. Figure 41 shows the dynamic voltage scaling function.
OUTPUT
NEW VID CODE
OLD VID CODE
OLD VID
NEW VID
VIDx
VID FOR
CH1 OR CH4
DVSx_INTVAL SETTING
25mV FOR CH1
(100mV FOR CH4)
10899-035
Figure 41. Dynamic Voltage Scaling
During the DVS transition period, the regulator is forced into
PWM mode operation, and OVP latch-off, SCP latch-off, and
hiccup protection are masked.
INTERNAL REGULATORS (VREG AND VDD)
The internal VREG regulator in the ADP5050 provides a stable
5.1 V power supply for the bias voltage of the MOSFET drivers.
The internal VDD regulator in the ADP5050 provides a stable
3.3 V power supply for internal control circuits. Connect a 1.0 µF
ceramic capacitor between VREG and ground, and connect
another 1.0 µF ceramic capacitor between VDD and ground.
The internal VREG and VDD regulators are active as long as
PVIN1 is available.
The internal VREG regulator can provide a total load of 95 mA
including the MOSFET driving current, and it can be used as
an always alive 5.1 V power supply for a small system current
demand. The current-limit circuit is included in the VREG
regulator to protect the circuit when the part is heavily loaded.
The VDD regulator is for internal circuit use and is not recom-
mended for other purposes.
SEPARATE SUPPLY APPLICATIONS
The ADP5050 supports separate input voltages for the four buck
regulators. This means that the input voltages for the four buck
regulators can be connected to different supply voltages.
The PVIN1 voltage provides the power supply for the internal
regulators and the control circuitry. Therefore, if the user plans
to use separate supply voltages for the buck regulators, the PVIN1
voltage must be above the UVLO threshold before the other
channels begin to operate.
Precision enabling can be used to monitor the PVIN1 voltage
and to delay the startup of the outputs to ensure that PVIN1 is
high enough to support the outputs in regulation. For more
information, see the Precision Enabling section.
The ADP5050 supports cascading supply operation for the four
buck regulators. As shown in Figure 42, PVIN2, PVIN3, and
PVIN4 are powered from the Channel 1 output. In this config-
uration, the Channel 1 output voltage must be higher than the
UVLO threshold for PVIN2, PVIN3, and PVIN4.
PVIN1
BUCK 1
BUCK 2
V
OUT1
PVIN2
TO
PVIN4
V
OUT2
TO V
OUT4
V
IN
10899-036
Figure 42. Cascading Supply Application