Datasheet

ManualsBrandsANALOG DEVICES ManualsPMICsPMIC - linear/switching voltage regulator Arbitrary function LFCSP 48 WQ (7x7)

5-Channel Integrated Power Solution with Quad

Buck Regulators and 200 mA LDO Regulator

Data Sheet

ADP5050

Rev. 0 Document Feedback

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FEATURES

Wide input voltage range: 4.5 V to 15 V

±1.5% output accuracy over full temperature range

250 kHz to 1.4 MHz adjustable switching frequency

Adjustable/fixed output options via factory fuse or I

C interface

C interface with interrupt on fault conditions

Power regulation

Channel 1 and Channel 2: programmable 1.2 A/2.5 A/4 A

sync buck regulators with low-side FET driver

Channel 3 and Channel 4: 1.2 A sync buck regulators

Channel 5: 200 mA low dropout (LDO) regulator

Single 8 A output (Channel 1 and Channel 2 operated in parallel)

Dynamic voltage scaling (DVS) for Channel 1 and Channel 4

Precision enable with 0.8 V accurate threshold

Active output discharge switch

Programmable phase shift in 90° steps

Individual channel FPWM/PSM mode selection

Frequency synchronization input or output

Optional latch-off protection on OVP/OCP failure

Power-good flag on selected channels

Low input voltage detection

Overheat detection on junction temperature

UVLO, OCP, and TSD protection

48-lead, 7 mm × 7 mm LFCSP package

−40°C to +125°C junction temperature

APPLICATIONS

Small cell base stations

FPGA and processor applications

Security and surveillance

Medical applications

TYPICAL APPLICATION CIRCUIT

CHANNEL 2

BUCK REGULATOR

(1.2A/2.5A/4A)

CHANNEL 3

BUCK REGULATOR

(1.2A)

OSCILLATOR

INT VREG

100mA

VREG

SYNC/MODE

FB1

BST1

SW1

DL1

PGND

DL2

SW2

BST2

FB2

BST3

SW3

FB3

PGND3

ALERT

BST4

SW4

FB4

PGND4

nINT

VREG

PVIN1

COMP1

EN1

PVIN2

COMP2

EN2

PVIN3

SS34

COMP3

EN3

VDDIO

PVIN4

COMP4

EN4

SCL

SDA

C10

C11

C12

C13

4.5V TO 15V

VOUT1

VOUT2

VOUT3

VOUT4

ILIM1

ILIM2

PWRGD

VREG

EXPOSED PAD

SS12

VDD

CHANNEL 5

200mA LDO

REGULATOR

FB5

PVIN5

EN5

VOUT5

C14

C15

VOUT5

1.7V TO 5.5V

ADP5050

CHANNEL 1

BUCK REGULATOR

(1.2A/2.5A/4A)

CHANNEL 4

BUCK REGULATOR

(1.2A)

10899-001

Figure 1.

GENERAL DESCRIPTION

The ADP5050 combines four high performance buck regulators

and one 200 mA low dropout (LDO) regulator in a 48-lead LFCSP

package that meets demanding performance and board space

requirements. The device enables direct connection to high input

voltages up to 15 V with no preregulators.

Channel 1 and Channel 2 integrate high-side power MOSFETs and

low-side MOSFET drivers. External NFETs can be used in low-side

power devices to achieve an efficiency optimized solution and

deliver a programmable output current of 1.2 A, 2.5 A, or 4 A.

Combining Channel 1 and Channel 2 in a parallel configuration

can provide a single output with up to 8 A of current.

Channel 3 and Channel 4 integrate both high-side and low-side

MOSFETs to deliver output current of 1.2 A.

The switching frequency of the ADP5050 can be programmed

or synchronized to an external clock. The ADP5050 contains a

precision enable pin on each channel for easy power-up sequencing

or adjustable UVLO threshold.

The ADP5050 integrates a general-purpose LDO regulator with

low quiescent current and low dropout voltage that provides up

to 200 mA of output current.

The optional I

C interface provides the user with flexible

configuration options, including adjustable and fixed output

voltage options, junction temperature overheat warning, low

input voltage detection, and dynamic voltage scaling (DVS).

Summary of content (60 pages)

PAGE 1
5-Channel Integrated Power Solution with Quad Buck Regulators and 200 mA LDO Regulator ADP5050 Data Sheet FEATURES TYPICAL APPLICATION CIRCUIT ADP5050 SYNC/MODE VREG VDD C1 INT VREG OSCILLATOR 100mA RT C0 FB1 PVIN1 4.5V TO 15V BST1 C2 COMP1 CHANNEL 1 BUCK REGULATOR (1.2A/2.5A/4A) SW1 EN1 DL2 RILIM1 RILIM2 Q2 CHANNEL 2 BUCK REGULATOR (1.2A/2.
PAGE 2
ADP5050 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Shutdown .................................................................... 26 Applications ....................................................................................... 1 Overheat Detection .................................................................... 26 Typical Application Circuit ....................................................
PAGE 3
Data Sheet ADP5050 Detailed Register Descriptions ......................................................42 Register 1: PCTRL (Channel Enable Control), Address 0x01 ................................................................................42 Register 2: VID1 (VID Setting for Channel 1), Address 0x02 ................................................................................42 Register 3: VID23 (VID Setting for Channel 2 and Channel 3), Address 0x03................................................
PAGE 4
ADP5050 Data Sheet DETAILED FUNCTIONAL BLOCK DIAGRAM CHANNEL 1 BUCK REGULATOR UVLO1 PVIN1 – 0.8V + + EN1 ACS1 – 1MΩ VREG HICCUP AND LATCH-OFF + OCP CLK1 – BST1 Q1 DRIVER + CMP1 – COMP1 0.8V FB1 + EA1 – CLK1 FREQUENCY FOLDBACK OVP LATCH-OFF + VID1 0.72V + 0.
PAGE 5
Data Sheet ADP5050 SPECIFICATIONS VIN = 12 V, VVREG = 5.1 V, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. Table 1.
PAGE 6
ADP5050 Data Sheet Parameter LOW INPUT VOLTAGE DETECTION Low Input Voltage Threshold Symbol Min Typ Max Unit Test Conditions/Comments VLVIN-TH 4.236 10.25 Low Input Voltage Threshold Range THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis 4.07 10.05 4.2 4.39 10.4 11.
PAGE 7
Data Sheet Parameter CHANNEL 2 SYNC BUCK REGULATOR FB2 Pin Fixed Output Options Adjustable Feedback Voltage Feedback Voltage Accuracy Feedback Bias Current SW2 Pin High-Side Power FET On Resistance Current-Limit Threshold Minimum On Time Minimum Off Time Low-Side Driver, DL2 Pin Rising Time Falling Time Sourcing Resistor Sinking Resistor Error Amplifier (EA), COMP2 Pin EA Transconductance Soft Start Soft Start Time Programmable Soft Start Range Hiccup Time COUT Discharge Switch On Resistance CHANNEL 3 SYN
PAGE 8
ADP5050 Parameter CHANNEL 4 SYNC BUCK REGULATOR FB4 Pin Fixed Output Options Adjustable Feedback Voltage Feedback Voltage Accuracy Feedback Bias Current SW4 Pin High-Side Power FET On Resistance Low-Side Power FET On Resistance Current-Limit Threshold Minimum On Time Minimum Off Time Error Amplifier (EA), COMP4 Pin EA Transconductance Soft Start Soft Start Time Programmable Soft Start Range Hiccup Time COUT Discharge Switch On Resistance Data Sheet Symbol Min VOUT4 2.
PAGE 9
Data Sheet ADP5050 I2C INTERFACE TIMING SPECIFICATIONS TA = 25°C, VVDD = 3.3 V, VVDDIO = 3.3 V, unless otherwise noted. Table 4. Parameter fSCL tHIGH tLOW tSU,DAT tHD,DAT tSU,STA tHD,STA tBUF tSU,STO tR tF tSP CB 2 Min Typ 0.6 1.3 100 0 0.6 0.6 1.3 0.6 20 + 0.1CB2 20 + 0.1CB2 0 Max 400 Unit kHz µs µs ns µs µs µs µs µs ns ns ns pF 0.
PAGE 10
ADP5050 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 5.
PAGE 11
Data Sheet ADP5050 48 47 46 45 44 43 42 41 40 39 38 37 EN3 SS34 COMP3 FB3 VREG SYNC/MODE VDD RT FB1 COMP1 SS12 EN1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADP5050 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 PVIN1 PVIN1 SW1 SW1 BST1 DL1 PGND DL2 BST2 SW2 SW2 PVIN2 NOTES 1. THE EXPOSED PAD MUST BE CONNECTED AND SOLDERED TO AN EXTERNAL GROUND PLANE.
PAGE 12
ADP5050 Pin No. 30 31 Mnemonic PGND DL1 32 33, 34 35, 36 BST1 SW1 PVIN1 37 38 EN1 SS12 39 40 41 COMP1 FB1 RT 42 43 VDD SYNC/MODE 44 45 46 47 VREG FB3 COMP3 SS34 48 EN3 EPAD Data Sheet Description Power Ground for Channel 1 and Channel 2. Low-Side FET Gate Driver for Channel 1. Connect a resistor from this pin to ground to program the current-limit threshold for Channel 1. High-Side FET Driver Power Supply for Channel 1. Switching Node Output for Channel 1. Power Input for the Internal 5.
PAGE 13
Data Sheet ADP5050 100 100 90 90 80 80 70 70 60 50 VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V VOUT = 5.0V 40 30 20 40 VOUT = 1.2V, FPWM VOUT = 1.2V, AUTO PWM/PSM VOUT = 1.8V, FPWM VOUT = 1.8V, AUTO PWM/PSM VOUT = 3.3V, FPWM VOUT = 3.3V, AUTO PWM/PSM 20 10 0 1 2 IOUT (A) 3 4 0 10899-003 0 0 90 90 80 80 70 70 EFFICIENCY (%) 100 60 50 VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V 30 20 1 10 Figure 8.
PAGE 14
ADP5050 Data Sheet 100 0.4 90 0.3 LINE REGULATION (%) 80 60 50 40 30 fSW = 300kHz fSW = 600kHz fSW = 1.0MHz 20 0.2 0 –0.1 –0.3 0.4 0.6 0.8 1.0 1.2 IOUT (A) –0.4 10899-009 0 0.1 –0.2 10 0 0.2 4.5 6.0 7.5 9.0 10.5 12.0 13.5 15.0 INPUT VOLTAGE (V) 10899-012 EFFICIENCY (%) 70 Figure 14. Channel 1 Line Regulation, VOUT = 3.3 V, IOUT = 4 A, fSW = 600 kHz, FPWM Mode Figure 11. Channel 3/Channel 4 Efficiency Curve, VIN = 12 V, VOUT = 1.8 V, FPWM Mode 0.4 100 90 0.
PAGE 15
Data Sheet ADP5050 6.0 0.4 5.5 0.3 QUIESCENT CURRENT (mA) FEEDBACK VOLTAGE ACCURACY (%) 0.5 0.2 0.1 0 –0.1 –0.2 –0.3 5.0 4.5 4.0 3.5 –20 10 40 70 100 130 TEMPERATURE (°C) 3.0 –50 10899-015 –0.5 –50 Figure 17. 0.8 V Feedback Voltage Accuracy vs. Temperature for Channel 1, Adjustable Output Model –25 0 25 50 75 TEMPERATURE (°C) 100 125 150 10899-018 –0.4 Figure 20. Quescient Current vs. Temperature (Includes PVIN1, PVIN2, PVIN3, and PVIN4) 2.0 75 65 SHUTDOWN CURRENT (µA) 1.
PAGE 16
ADP5050 Data Sheet 100 7 RILIM = 22kΩ 6 RILIM = OPEN NOISE (µV/√Hz) CURRENT LIMIT (A) 10 5 4 3 1 VOUT = 1.2V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V RILIM = 47kΩ 2 0.1 4 6 8 10 12 14 16 INPUT VOLTAGE (V) 0.01 10899-021 0 10 10k 100k Figure 23. Channel 1/Channel 2 Current Limit vs. Input Voltage Figure 26. Channel 5 (LDO Regulator) Output Noise Spectrum, VIN = 5 V, COUT = 1 µF, IOUT = 10 mA 200 180 180 160 CH3/CH4 80 60 100 60 VOUT = 1.
PAGE 17
Data Sheet 0 ADP5050 PVIN5 = PVIN5 = PVIN5 = PVIN5 = PVIN5 = PVIN5 = –10 –20 4.0V; IOUT = 1mA 3.6V, IOUT = 1mA 4.0V, IOUT = 100mA 3.6V, IOUT = 100mA 4.0V, IOUT = 200mA 3.6V, IOUT = 200mA 1 VOUT PSRR (dB) –30 –40 –50 –60 IOUT –70 –80 –90 100 1k 10k 100k 1M 10M FREQUENCY (Hz) CH1 50.0mV BW M100µs A CH1 –22.0mV CH4 2.00A Ω 10899-030 10 10899-027 4 –100 Figure 32. Channel 1/Channel 2 Load Transient, 1 A to 4 A, VIN = 12 V, VOUT = 3.3 V, fSW = 600 kHz, L = 2.
PAGE 18
ADP5050 Data Sheet VIN 1 VOUT VOUT 1 SW EN 3 2 2 IOUT IOUT A CH2 2.80V 10899-033 M400µs CH2 5.00V BW CH4 1.00A Ω BW CH1 10.0V BW CH3 1.00V BW CH1 500mV BW Figure 35. Startup with Precharged Output, VIN = 12 V, VOUT = 3.3 V M10.0ms A CH1 CH2 10.0V BW CH4 5.00A Ω BW 970mV 10899-136 4 4 Figure 38. Short-Circuit Protection Recovery, VIN = 12 V, VOUT = 1.2 V, fSW = 600 kHz, L = 1 µH, COUT = 47 µF × 2 VOUT VOUT 1 IOUT 4 EN 2 M10.0ms A CH1 CH2 5.00V BW CH4 5.
PAGE 19
Data Sheet ADP5050 THEORY OF OPERATION The ADP5050 is a micropower management unit that combines four high performance buck regulators with a 200 mA low dropout (LDO) regulator in a 48-lead LFCSP package to meet demanding performance and board space requirements. The device enables direct connection to high input voltages up to 15 V with no preregulators to make applications simpler and more efficient.
PAGE 20
ADP5050 Data Sheet ADJUSTABLE AND FIXED OUTPUT VOLTAGES INTERNAL REGULATORS (VREG AND VDD) The ADP5050 provides adjustable and fixed output voltage settings via the I2C interface or factory fuse. For the adjustable output settings, use an external resistor divider to set the desired output voltage via the feedback reference voltage (0.8 V for Channel 1 to Channel 4, and 0.5 V for Channel 5). The internal VREG regulator in the ADP5050 provides a stable 5.
PAGE 21
Data Sheet ADP5050 The buck regulators in Channel 1 and Channel 2 integrate 4 A high-side power MOSFETs and low-side MOSFET drivers. The N-channel MOSFETs selected for use with the ADP5050 must be able to work with the synchronized buck regulators. In general, a low RDSON N-channel MOSFET can be used to achieve higher efficiency; dual MOSFETs in one package (for both Channel 1 and Channel 2) are recommended to save space on the PCB. For more information, see the Low-Side Power Device Selection section.
PAGE 22
ADP5050 Data Sheet Phase Shift By default, the phase shift between Channel 1 and Channel 2 and between Channel 3 and Channel 4 is 180° (see Figure 45). This value provides the benefits of out-of-phase operation by reducing the input ripple current and lowering the ground noise.
PAGE 23
Data Sheet ADP5050 SOFT START VIN The buck regulators in the ADP5050 include soft start circuitry that ramps the output voltage in a controlled manner during startup, thereby limiting the inrush current. The soft start time is typically fixed at 2 ms for each buck regulator when the SS12 and SS34 pins are tied to VREG. PVIN1 PVIN2 VREG SS12 To set the soft start time to a value of 2 ms, 4 ms, or 8 ms, connect a resistor divider from the SS12 or SS34 pin to the VREG pin and ground (see Figure 49).
PAGE 24
ADP5050 Data Sheet CURRENT-LIMIT PROTECTION HICCUP PROTECTION The buck regulators in the ADP5050 include peak current-limit protection circuitry to limit the amount of positive current flowing through the high-side MOSFET. The peak current limit on the power switch limits the amount of current that can flow from the input to the output. The programmable current-limit threshold feature allows for the use of small size inductors for low current applications.
PAGE 25
Data Sheet ADP5050 The short-circuit latch-off status can be read from Register 12, LCH_STATUS. To clear the status bit, write a 1 to the bit (provided that the fault no longer persists). The status bit is latched until a 1 is written to the bit or the part is reset by the internal VDD power-on reset signal. Note that short-circuit latch-off mode does not work if hiccup protection is disabled.
PAGE 26
ADP5050 Data Sheet THERMAL SHUTDOWN LOW INPUT VOLTAGE DETECTION If the ADP5050 junction temperature exceeds 150°C, the thermal shutdown circuit turns off the IC except for the internal linear regulators. Extreme junction temperatures can be the result of high current operation, poor circuit board design, or high ambient temperature. A 15°C hysteresis is included so that the ADP5050 does not return to operation after thermal shutdown until the on-chip temperature falls below 135°C.
PAGE 27
Data Sheet ADP5050 I2C INTERFACE The ADP5050 includes an I2C-compatible serial interface for control of the power management blocks and for readback of system status (see Figure 57). The I2C interface operates at clock frequencies of up to 400 kHz. VDD VDDIO UVLO_VDDIO VDDIO VDDIO VDD VDD VDD VDDIO LEVEL SHIFTER I2C REGISTER The default 7-bit I2C chip address for the ADP5050 is 0x48 (1001000 in binary).
PAGE 28
ADP5050 Data Sheet I2C INTERFACE TIMING DIAGRAMS The subaddress is used to select one of the user registers in the ADP5050. The ADP5050 sends data to and from the register specified by the subaddress. Figure 59 shows the timing diagram for the I2C write operation. Figure 60 shows the timing diagram for the I2C read operation.
PAGE 29
Data Sheet ADP5050 APPLICATIONS INFORMATION ADIsimPower DESIGN TOOL The ADP5050 is supported by the ADIsimPower™ design tool set. ADIsimPower is a collection of tools that produce complete power designs optimized for a specific design goal. The tools enable the user to generate a full schematic and bill of materials and to calculate performance in minutes.
PAGE 30
ADP5050 Data Sheet SOFT START SETTING Table 13. Recommended Inductors The buck regulators in the ADP5050 include soft start circuitry that ramps the output voltage in a controlled manner during startup, thereby limiting the inrush current. To set the soft start time to a value of 2 ms, 4 ms, or 8 ms, connect a resistor divider from the SS12 or SS34 pin to the VREG pin and ground (see the Soft Start section).
PAGE 31
Data Sheet ADP5050 The output voltage ripple is determined by the ESR of the output capacitor and its capacitance value. Use the following equations to select a capacitor that can meet the output ripple requirements: COUT _ RIPPLE = RESR = ∆I L 8 × f SW × ∆VOUT _ RIPPLE When the high-side MOSFET is turned off, the low-side MOSFET supplies the inductor current. For low duty cycle applications, the low-side MOSFET supplies the current for most of the period.
PAGE 32
ADP5050 Data Sheet COMPENSATION COMPONENTS DESIGN For the peak current-mode control architecture, the power stage can be simplified as a voltage controlled current source that supplies current to the output capacitor and load resistor. The simplified loop is composed of one domain pole and a zero contributed by the output capacitor ESR.
PAGE 33
Data Sheet ADP5050 Switching Loss (PSW) LDO Regulator Power Dissipation Switching losses are associated with the current drawn by the driver to turn the power devices on and off at the switching frequency. Each time a power device gate is turned on or off, the driver transfers a charge from the input supply to the gate, and then from the gate to ground.
PAGE 34
ADP5050 Data Sheet DESIGN EXAMPLE This section provides an example of the step-by-step design procedures and the external components required for Channel 1. Table 15 lists the design requirements for this example. Table 15. Example Design Requirements for Channel 1 Parameter Input Voltage Output Voltage Output Current Output Ripple Load Transient Specification VPVIN1 = 12 V ± 5% VOUT1 = 1.
PAGE 35
Data Sheet ADP5050 COUT _ RIPPLE = ∆I L 100 120 8 × f SW × ∆VOUT _ RIPPLE 80 90 60 60 40 30 20 0 ∆VOUT _ RIPPLE ∆I L MAGNITUDE (dB) R ESR = Figure 62 shows the Bode plot for the 1.2 V output rail. The cross frequency is 62 kHz, and the phase margin is 58°. Figure 63 shows the load transient waveform. The calculated capacitance, COUT_RIPPLE, is 20.8 µF, and the calculated RESR is 10 mΩ.
PAGE 36
ADP5050 Data Sheet RECOMMENDED EXTERNAL COMPONENTS Table 16 lists the recommended external components for 4 A applications used with Channel 1 and Channel 2 of the ADP5050. Table 17 lists the recommended external components for 1.2 A applications used with Channel 3 and Channel 4. Table 16. Recommended External Components for Typical 4 A Applications, Channel 1 and Channel 2 (±1% Output Ripple, ±7.
PAGE 37
Data Sheet ADP5050 CIRCUIT BOARD LAYOUT RECOMMENDATIONS • • • • • Place the input capacitor, inductor, MOSFET, output capacitor, and bootstrap capacitor close to the IC. Use short, thick traces to connect the input capacitors to the PVINx pins, and use dedicated power ground to connect the input and output capacitor grounds to minimize the connection length. Use several high current vias, if required, to connect PVINx, PGNDx, and SWx to other power planes.
PAGE 38
ADP5050 Data Sheet TYPICAL APPLICATION CIRCUITS ADP5050 VREG SYNC/MODE VREG VDD C0 1.0µF C1 1.0µF INT VREG OSCILLATOR 100mA RT 31.6kΩ FB1 PVIN1 12V nINT BST1 C2 10µF COMP1 6.81kΩ EN1 2.7nF VREG CHANNEL 1 BUCK REGULATOR (1.2A/2.5A/4A) SW1 5V REG DL1 SS12 COMP2 VREG 2.2µH C4 47µF Q1 1.1V TO 1.3V/2.5A (DVS) SiA906EDJ (46mΩ) VCORE PROCESSOR VDDIO DL2 6.81kΩ EN2 CHANNEL 2 BUCK REGULATOR (1.2A/2.5A/4A) COMP3 6.81kΩ EN3 5V REG L2 VOUT2 4.7µH C7 47µF SW2 BST2 C6 0.
PAGE 39
Data Sheet ADP5050 ADP5050 VREG SYNC/MODE VREG VDD C0 1.0µF C1 1.0µF INT VREG OSCILLATOR 100mA RT 31.6kΩ 10kΩ FB1 PVIN1 12V 4.99kΩ BST1 C2 10µF COMP1 2.7nF 10kΩ EN1 VREG SW1 CHANNEL 1 BUCK REGULATOR (1.2A/2.5A/4A) 5V REG PGND PVIN2 DL2 L1 VOUT1 1.5µH C4 47µF Q1 DL1 SS12 C5 10µF COMP2 2.7nF 10kΩ EN2 C3 0.1µF 1.2V/4A VCORE C16 47µF Si7232DN (16.4mΩ) 22kΩ FPGA 22kΩ AUXILIARY VOLTAGE Q2 CHANNEL 2 BUCK REGULATOR (1.2A/2.5A/4A) 5V REG L2 VOUT2 2.2µH C7 47µF SW2 BST2 C6 0.
PAGE 40
ADP5050 Data Sheet ADP5050 VREG SYNC/MODE VREG VDD C1 1.0µF C0 1.0µF PVIN1 INT VREG OSCILLATOR 100mA RT 31.6kΩ 10kΩ FB1 12V 4.99kΩ BST1 C2 10µF COMP1 2.7nF CHANNEL 1 BUCK REGULATOR (1.2A/2.5A/4A) 10kΩ EN1 VREG 100kΩ SW1 DL1 SS12 C5 10µF Si7232DN (16.4mΩ) Q1 PGND DL2 CHANNEL 2 BUCK REGULATOR (1.2A/2.5A/4A) 5V REG 2.7nF VREG 6.81kΩ EN3 C16 100µF 22kΩ L2 1.5µH C6 0.1µF FB2 PVIN3 COMP3 C4 100µF 1.2V/8A 22kΩ SW2 BST2 EN2 C8 10µF VOUT1 Q2 PVIN2 COMP2 L1 1.
PAGE 41
Data Sheet ADP5050 REGISTER MAP Table 18. Register Map Reg.
PAGE 42
ADP5050 Data Sheet DETAILED REGISTER DESCRIPTIONS This section describes the bit functions of each register used by the ADP5050. To reset a register, the internal VDD power-on reset signals must be low, unless otherwise noted. REGISTER 1: PCTRL (CHANNEL ENABLE CONTROL), ADDRESS 0x01 Register 1 is used to enable and disable the operation of each channel. The on or off status of a channel is controlled by the CHx_ON bit in this register and the external hardware enable pin for the channel (logical AND).
PAGE 43
Data Sheet ADP5050 REGISTER 3: VID23 (VID SETTING FOR CHANNEL 2 AND CHANNEL 3), ADDRESS 0x03 Register 3 is used to set the output voltage for Channel 2 and Channel 3. Table 23. Register 3 Bit Assignments Bit 7 Reserved Bit 6 Bit 5 VID3[2:0] Bit 4 Bit 3 Reserved Bit 2 Bit 1 VID2[2:0] Bit 0 Table 24. VID23 Register, Bit Function Descriptions Bits 7 [6:4] Bit Name Reserved VID3[2:0] Access R/W R/W 3 [2:0] Reserved VID2[2:0] R/W R/W Description Reserved.
PAGE 44
ADP5050 Data Sheet REGISTER 5: DVS_CFG (DVS CONFIGURATION FOR CHANNEL 1 AND CHANNEL 4), ADDRESS 0x05 Register 5 is used to configure dynamic voltage scaling (DVS) for Channel 1 and Channel 4 (see the Dynamic Voltage Scaling (DVS) section). Table 27. Register 5 Bit Assignments Bit 7 Reserved Bit 6 DVS4_ON Bit 5 Bit 4 DVS4_INTVAL[1:0] Bit 3 Reserved Bit 2 DVS1_ON Table 28.
PAGE 45
Data Sheet ADP5050 REGISTER 6: OPT_CFG (FPWM/PSM MODE AND OUTPUT DISCHARGE FUNCTION CONFIGURATION), ADDRESS 0x06 Register 6 is used to configure the operational mode and the discharge switch setting for Channel 1 to Channel 4. The PSMx_ON bit setting for each channel is in effect when the SYNC/MODE pin is high (or when SYNC/MODE is configured as a clock input or output).
PAGE 46
ADP5050 Data Sheet REGISTER 7: LCH_CFG (SHORT-CIRCUIT LATCH-OFF AND OVERVOLTAGE LATCH-OFF CONFIGURATION), ADDRESS 0x07 Register 7 is used to enable and disable the latch-off function for short-circuit protection (SCP) and overvoltage protection (OVP). When the SCP or OVP latch-off function is enabled, the CHx_LCH bit in Register 12 is set after an error condition occurs (see the Latch-Off Protection section).
PAGE 47
Data Sheet ADP5050 REGISTER 8: SW_CFG (SWITCHING FREQUENCY AND PHASE SHIFT CONFIGURATION), ADDRESS 0x08 Register 8 is used to configure the switching frequency for Channel 1 and Channel 3 and to configure the phase shift for Channel 2, Channel 3, and Channel 4 with respect to Channel 1 (0˚). The default values for the Channel 1 and Channel 3 switching frequencies can be programmed by factory fuse. Table 33.
PAGE 48
ADP5050 Data Sheet REGISTER 9: TH_CFG (TEMPERATURE WARNING AND LOW VIN WARNING THRESHOLD CONFIGURATION), ADDRESS 0x09 Register 9 is used to configure the junction temperature overheat detection threshold and the low input voltage detection threshold. When these thresholds are enabled, the TEMP_INT and LVIN_INT status bits in Register 14 are set if the thresholds are exceeded. Table 35. Register 9 Bit Assignments Bit 7 Bit 6 Reserved Bit 5 Bit 4 TEMP_TH[1:0] Bit 3 Bit 2 Bit 1 LVIN_TH[3:0] Table 36.
PAGE 49
Data Sheet ADP5050 REGISTER 10: HICCUP_CFG (HICCUP CONFIGURATION), ADDRESS 0x0A Register 10 is used to configure the SYNC/MODE pin as a synchronization input or output and to configure hiccup protection for each channel. The default value for hiccup protection can be programmed by factory fuse (hiccup function enabled or disabled for all four buck regulators). Table 37.
PAGE 50
ADP5050 Data Sheet REGISTER 11: PWRGD_MASK (CHANNEL MASK CONFIGURATION FOR PWRGD PIN), ADDRESS 0x0B Register 11 is used to mask or unmask the power-good status of Channel 1 to Channel 4; when unmasked, a power-good failure on any of these channels triggers the PWRGD pin. The output of the PWRGD pin represents the logical AND of all unmasked PWRGD signals; that is, the PWRGD pin is pulled low by any PWRGD signal failure. There is a 1 ms validation delay time before the PWRGD pin goes high.
PAGE 51
Data Sheet ADP5050 REGISTER 12: LCH_STATUS (LATCH-OFF STATUS READBACK), ADDRESS 0x0C Register 12 contains latched fault flags for thermal shutdown and channel latch-off caused by an OVP or SCP condition. Latched flags are not reset when the fault disappears but are cleared only when a 1 is written to the appropriate bit (provided that the fault no longer persists). Table 41.
PAGE 52
ADP5050 Data Sheet REGISTER 14: INT_STATUS (INTERRUPT STATUS READBACK), ADDRESS 0x0E Register 14 contains the interrupt status for the following events: junction temperature overheat warning, low input voltage warning, and power-good signal failure on Channel 1 to Channel 4. When any of these unmasked events occur, the nINT pin is pulled low to indicate a fault condition. (Masking of these events is configured in Register 15.) To determine the cause of the fault, read this register.
PAGE 53
Data Sheet ADP5050 REGISTER 15: INT_MASK (INTERRUPT MASK CONFIGURATION), ADDRESS 0x0F Register 15 is used to mask or unmask various warnings for use by the interrupt (nINT) pin. When any bit in this register is masked, the associated event does not trigger the nINT pin. Table 47. Register 15 Bit Assignments Bit 7 Bit 6 Reserved Bit 5 MASK_TEMP Bit 4 MASK_LVIN Bit 3 MASK_PWRG4 Bit 2 MASK_PWRG3 Bit 1 MASK_PWRG2 Bit 0 MASK_PWRG1 Table 48.
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ADP5050 Data Sheet FACTORY PROGRAMMABLE OPTIONS Table 51 through Table 64 list the options that can be programmed into the ADP5050 when it is ordered from Analog Devices. For a list of the default options, see Table 65. To order a device with options other than the default options, contact your local Analog Devices sales or distribution representative. Table 51. Output Voltage Options for Channel 1 (Fixed Output Options: 0.85 V to 1.
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Data Sheet ADP5050 Table 56.
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ADP5050 Data Sheet Table 63. Overvoltage Latch-Off Options for the Four Buck Regulators Option Option 0 Option 1 Description Latch-off function disabled for output overvoltage events (default) Latch-off function enabled for output overvoltage events Table 64.
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Data Sheet ADP5050 OUTLINE DIMENSIONS 0.30 0.25 0.20 PIN 1 INDICATOR 37 36 48 1 0.50 BSC TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 5.60 SQ 5.55 13 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF SEATING PLANE *5.65 EXPOSED PAD 24 PIN 1 INDICATOR 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT TO JEDEC STANDARDS MO-220-WKKD-2 WITH THE EXCEPTION OF THE EXPOSED PAD DIMENSION.
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ADP5050 Data Sheet NOTES Rev.
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Data Sheet ADP5050 NOTES Rev.
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ADP5050 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10899-0-5/13(0) Rev.