Datasheet

Data Sheet ADP5041
Rev. 0 | Page 35 of 40
The inductor losses are estimated (without core losses) by
L
RMSOUT1
L
DCRIP ×≅
2
)(
(4)
where:
DCR
L
is the inductor series resistance.
I
OUT1(RMS)
is the rms load current of the buck regulator.
/12+1
)(
rII
OUT1
RMSOUT1
×=
(5)
where r is the normalized inductor ripple current.
r ≈ V
OUT1
× (1-D)/(I
OUT1
× L × f
SW
) (6)
where:
L is inductance.
f
SW
is switching frequency.
D is duty cycle.
D = V
OUT1
/V
IN1
(7)
The
ADP5041 buck regulator power dissipation, P
DBUCK
, includes
the power switch conductive losses, the switch losses, and the
transition losses of each channel. There are other sources of
loss, but these are generally less significant at high output load
currents, where the thermal limit of the application is. Equation 8
shows the calculation made to estimate the power dissipation in
the buck regulator.
P
DBUCK
= P
COND
+ P
SW
+ P
TRAN
(8)
The power switch conductive losses are due to the output current,
I
OUT1
, flowing through the PMOSFET and the NMOSFET power
switches that have internal resistance, R
DSON-P
and R
DSON-N
. The
amount of conductive power loss is found by:
P
COND
= [R
DSON-P
× D + R
DSON-N
× (1 − D)] × I
OUT1
2
(9)
For the
ADP5041, at 125°C junction temperature and VIN1 =
3.6 V, R
DSON-P
is approximately 0.2 Ω, and R
DSON-N
is approximately
0.16 Ω. At VIN1 = 2.3 V, these values change to 0.31 Ω and
0.21 Ω respectively, and at VIN1 = 5.5 V, the values are 0.16 Ω
and 0.14 Ω, respectively.
Switching losses are associated with the current drawn by the
driver to turn on and turn off the power devices at the switching
frequency. The amount of switching power loss is given by:
P
SW
= (C
GATE-P
+ C
GATE-N
) × V
IN1
2
× f
SW
(10)
where:
C
GAT E-P
is the PMOSFET gate capacitance.
C
GAT E-N
is the NMOSFET gate capacitance.
For the
ADP5041, the total of (C
GAT E-P
+ C
GAT E-N
) is approximately
150 pF.
The transition losses occur because the PMOSFET cannot be
turned on or off instantaneously, and the SW node takes some
time to slew from near ground to near V
OUT1
(and from V
OUT1
to
ground). The amount of transition loss is calculated by:
P
TRAN
= V
IN1
× I
OUT1
× (t
RISE
+ t
FALL
) × f
SW
(11)
where t
RISE
and t
FALL
are the rise time and the fall time of the
switching node, SW. For the
ADP5041, the rise and fall times of
SW are in the order of 5 ns.
If the preceding equations and parameters are used for
estimating the converter efficiency, it must be noted that the
equations do not describe all of the converter losses, and the
parameter values given are typical numbers. The converter
performance also depends on the choice of passive components
and board layout; therefore, a sufficient safety margin should be
included in the estimate.
LDO Regulator Power Dissipation
The power loss of a LDO regulator is given by:
P
DLDO
= [(V
IN
− V
OUT
) × I
LOAD
] + (V
IN
× I
GND
) (12)
where:
I
LOAD
is the load current of the LDO regulator.
V
IN
and V
OUT
are input and output voltages of the LDO,
respectively.
I
GND
is the ground current of the LDO regulator.
Power dissipation due to the ground current is small and it
can be ignored.
The total power dissipation in the
ADP5041 simplifies to:
P
D
= {[P
DBUCK
+ P
DLDO1
+ P
DLDO2
]} (13)
Junction Temperature
In cases where the board temperature, T
A
, is known, the
thermal resistance parameter, θ
JA
, can be used to estimate the
junction temperature rise. T
J
is calculated from T
A
and P
D
using
the formula
T
J
= T
A
+ (P
D
× θ
JA
) (14)
The typical θ
JA
value for the 20-lead, 4 mm × 4 mm LFCSP is
38°C/W (see Table 7). A very important factor to consider is
that θ
JA
is based on a 4-layer, 4 inch × 3 inch, 2.5 oz copper, as
per JEDEC standard, and real applications may use different
sizes and layers. To remove heat from the device, it is important
to maximize the use of copper. Copper exposed to air dissipates
heat better than copper used in the inner layers. The exposed
pad (EP) should be connected to the ground plane with several
vias as shown in Figure 114.
If the case temperature can be measured, the junction temperature
is calculated by
T
J
= T
C
+ (P
D
× θ
JC
) (15)
where:
T
C
is the case temperature.
θ
JC
is the junction-to-case thermal resistance provided in
Table 7.
When designing an application for a particular ambient
temperature range, calculate the expected
ADP5041 power
dissipation (P
D
) due to the losses of all channels by using
Equation 8 to Equation 13. From this power calculation, the
junction temperature, T
J
, can be estimated using Equation 14.