Datasheet

Data Sheet ADP5041
Rev. 0 | Page 29 of 40
RSTO
nRSTO
VOUT2
VOUT2
VOUT2
0V
1V
0V
1V
0V
09652-093
V
TH
V
TH
t
RP
t
RP
t
RD
t
RD
Figure 104. Reset Timing Diagram
The ADP5041 has a reset threshold programming input pin,
VTHR, to monitor a supply rail.
The reset threshold voltage at VTHR input is typically 0.5 V.
To monitor a voltage greater than 0.5 V, connect a resistor
divider network to the device as shown in Figure 105, where






+
=
2
21
5.0
R
RR
VV
MONITORED
09652-094
V
REF
= 0.5V
VTHR
MONITORED VOLTAGE
R1
R2
Figure 105. External Reset Threshold Programming
Do not allow the VTHR input to float or to be grounded.
Connect it to a supply voltage greater than its specified
threshold voltage. A small capacitor can be added on VTHR to
improve the noise rejection and to prevent false reset
generation.
The
ADP5041 can be factory programmed to a 2.25 V or 3.6 V
UVLO threshold. When monitoring the input supply voltage, if
the selected reset threshold is below the UVLO level, the reset
output, nRSTO, is asserted low as soon as the input voltage falls
below the UVLO threshold. Below the UVLO threshold, the
reset output is maintained low down to ~1 V input voltage. This
is to ensure that the reset output is not released when there is
sufficient voltage on the rail supplying a processor to restart the
processor operations.
Manual Reset Input
The ADP5041 features a manual reset input (
MR
) which, when
driven low, asserts the reset output. When
MR
transitions from
low to high, the reset remains asserted for the duration of the
reset active timeout period before deasserting. The
MR
input
has a 52 kΩ, internal pull-up connected to AVIN, so that the
input is always high when unconnected. An external push-
button switch can be connected between
MR
and ground so
that the user can generate a reset. Debounce circuitry for this
purpose is integrated on chip. Noise immunity is provided on the
MR
input, and fast negative-going transients of up to 100 ns
(typical) are ignored. A 0.1 µF capacitor between
MR
and ground
provides additional noise immunity.
Watchdog Input
The ADP5041 features a watchdog timer that monitors
microprocessor activity. The watchdog timer circuit is cleared
with every low-to-high or high-to-low logic transition on the
watchdog input pin (WDI), which detects pulses as short as 80 ns.
If the timer counts through the preset watchdog timeout period
(t
WDI
), an output reset is asserted. The microprocessor is required
to toggle the WDI pin to avoid being reset. Failure of the
microprocessor to toggle WDI within the timeout period,
therefore, indicates a code execution error, and the reset pulse
generated restarts the microprocessor in a known state.
As well as logic transitions on WDI, the watchdog timer is also
cleared by a reset assertion due to an undervoltage condition on
the monitored rail. When reset is asserted, the watchdog timer
is cleared and does not begin counting again until reset deasserts.
The watchdog timer can be disabled by leaving WDI floating or
by three-stating the WDI driver.
The ADP5041 can be factory programmed to two possible
watchdog timer values as indicated in Table 18.
WDI
1V
0V
0V
0V
09652-095
t
RP
t
WD
t
RP
V
TH
V
SENSED
nRSTO
Figure 106. Watchdog Timing Diagram