Datasheet

ManualsBrandsANALOG DEVICES ManualsPMICsPMIC - linear/switching voltage regulator Arbitrary function LFCSP 20 WQ (4x4)

Micro PMU with 1.2 A Buck, Two 300 mA LDOs,

Supervisory, Watchdog, and Manual Reset

Data Sheet

ADP5041

ev. 0

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FEATURES

Input voltage range: 2.3 V to 5.5 V

One 1.2 A buck regulator

Two 300 mA LDOs

20-lead, 4 mm × 4 mm LFCSP package

Overcurrent and thermal protection

Soft start

Undervoltage lockout

Open-drain processor reset with externally adjustable

threshold monitoring

Guaranteed reset output valid to V

AVIN

= 1 V

Manual reset input

Watchdog refresh input

Buck key specifications

Output voltage range: 0.8 V to 3.8 V

Current mode topology for excellent transient response

3 MHz operating frequency

Peak efficiency up to 96%

Uses tiny multilayer inductors and capacitors

Mode pin selects forced PWM or auto PWM/PSM mode

100% duty cycle low dropout mode

LDOs key specifications

Output voltage range: 0.8 V to 5.2 V

Low input supply voltage from 1.7 V to 5.5 V

Stable with 2.2 μF ceramic output capacitors

High PSRR

Low output noise

Low dropout voltage

−40°C to +125°C junction temperature range

FUNCTIONAL BLOCK DIAGRAM

EN_BK

09652-001

FB2

FB3

2.2µF

VOUT2

AVIN

VBIAS

VOUT1

FB1

1µH

IN1

= 2.3V TO

5.5V

4.7µF

SUPERVISOR

µP

nRSTO

WDI

VTHR

FILT

= 30Ω

IN2

= 1.7V

TO 5.5V

VIN1

OFF

EN1

VIN2

1µF

EN2

EN3

VIN3

IN3

= 1.7V

TO 5.5V

EN_LDO2

LDO2

(ANALOG)

BUCK

AGND

OUT1

1.2A

10µF

PGND

FPWM

PSM/PWM

MODE

OUT2

300mA

OUT3

300mA

VOUT3

LDO1

(DIGITAL)

EN_LDO1

Figure 1.

GENERAL DESCRIPTION

The ADP5041 combines one high performance buck regulator

and two low dropout regulators (LDO) in a small 20-lead

LFCSP to meet demanding performance and board space

requirements.

The high switching frequency of the buck regulator enables

use of tiny multilayer external components and minimizes

board space.

When the MODE pin is set to logic high, the buck regulator

operates in forced PWM mode. When the MODE pin is set to

logic low, the buck regulator operates in PWM mode when the

load is around the nominal value. When the load current falls

below a predefined threshold, the regulator operates in power

save mode (PSM), improving the light load efficiency. The low

quiescent current, low dropout voltage, and wide input voltage

range of the ADP5041 LDOs extend the battery life of portable

devices. The ADP5041 LDOs maintain a power supply rejection

greater than 60 dB for frequencies as high as 10 kHz while

operating with a low headroom voltage.

Each regulator in the ADP5041 is activated by a high level on

the respective enable pin. The output voltages of the regulators

and the reset threshold are programmed through external resistor

dividers to address a variety of applications. The ADP5041

contains supervisory circuits that monitor power supply voltage

levels and code execution integrity in microprocessor-based

systems. They also provide power-on reset signals. An on-chip

watchdog timer can reset the microprocessor if it fails to strobe

within a preset timeout period.

Summary of content (40 pages)

PAGE 1
Micro PMU with 1.2 A Buck, Two 300 mA LDOs, Supervisory, Watchdog, and Manual Reset ADP5041 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM VOUT1 RFILT = 30Ω L1 1µH AVIN SW VBIAS VIN1 = 2.3V TO 5.5V FB1 VOUT1 AT 1.2A C6 10µF R1 R2 VIN1 PGND C1 4.7µF EN_BK ON VIN2 C2 1µF LDO1 (DIGITAL) ON PSM/PWM VOUT2 VOUT2 AT 300mA R3 FB2 EN_LDO1 OFF FPWM MODE EN1 OFF VIN2 = 1.7V TO 5.5V BUCK R4 C5 2.2µF EN2 nRSTO VBIAS MR SUPERVISOR µP WDI VTHR ON OFF VIN3 = 1.7V TO 5.
PAGE 2
ADP5041 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Buck Section................................................................................ 27 Functional Block Diagram .............................................................. 1 LDO Section ............................................................................... 28 General Description ..............................................................
PAGE 3
Data Sheet ADP5041 SPECIFICATIONS GENERAL SPECIFICATIONS AVIN, VIN1 = 2.3 V to 5.5 V; AVIN, VIN1 ≥VIN2, VIN3; VIN2, VIN3 = 1.7 V to 5.5 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. Table 1.
PAGE 4
ADP5041 Data Sheet Parameter WATCHDOG INPUT Watchdog Timeout Period Option 0 Option 1 WDI Pulse Width WDI Input Threshold Min Typ Max Unit Test Conditions/Comments 81.6 1.28 80 102 1.6 122.4 1.92 ms sec ns VIL = 0.4 V, VIH = 1.2 V 1.2 V 20 −15 µA µA VWDI = VCC, time average VWDI = 0 V, time average µs ns kΩ Ns VCC = 5 V 0.
PAGE 5
Data Sheet ADP5041 LDO1, LDO2 SPECIFICATIONS VIN2, VIN3 = (VOUT2,VOUT3 + 0.5 V) or 1.7 V (whichever is greater) to 5.5 V; AVIN, VIN1 ≥ VIN2, VIN3; CIN = 1 µF, COUT = 2.2 µF; TJ= −40°C to +125°C for minimum/maximum specifications and TA = 25°C for typical specifications, unless otherwise noted. 1 Table 4. Parameter INPUT VOLTAGE RANGE OPERATING SUPPLY CURRENT Bias Current per LDO 2 Typ Max 5.
PAGE 6
ADP5041 Data Sheet INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS Table 5. Parameter INPUT CAPACITANCE (BUCK) 1 OUTPUT CAPACITANCE (BUCK) 2 INPUT AND OUTPUT CAPACITANCE 3 (LDO1, LDO2) CAPACITOR ESR Symbol CMIN1 CMIN2 CMIN34 RESR Test Conditions/Comments TJ = −40°C to +125°C TJ = −40°C to +125°C TJ = −40°C to +125°C TJ = −40°C to +125°C Min 4.7 7 0.70 0.001 Typ Max 40 40 1 Unit µF µF µF Ω The minimum input capacitance should be greater than 4.7 µF over the full range of operating conditions.
PAGE 7
Data Sheet ADP5041 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter AVIN to AGND VIN1 to AVIN PGND to AGDN VIN2, VIN3, VOUTx, ENx, MODE, MR, WDI, nRSTO, FBx, VTHR, SW to AGND SW to PGND Storage Temperature Range Operating Junction Temperature Range Soldering Conditions ESD Human Body Model ESD Charged Device Model ESD Machine Model Rating −0.3 V to +6 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to (AVIN + 0.3 V) −0.3 V to (VIN1 + 0.
PAGE 8
ADP5041 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADP5041 20 19 18 17 16 MR WDI VTHR MODE EN2 TOP VIEW (Not to Scale) 15 14 13 12 11 1 2 3 4 5 FB2 VOUT2 VIN2 FB1 VOUT1 NOTES 1. EXPOSED PAD MUST BE CONNECTED TO SYSTEM GROUND PLANE. 09652-002 AVIN 6 VIN1 7 SW 8 PGND 9 EN1 10 FB3 VOUT3 VIN3 EN3 nRSTO Figure 2. Pin Configuration—View from Top of the Die Table 8. Pin Function Descriptions Pin No.
PAGE 9
Data Sheet ADP5041 TYPICAL PERFORMANCE CHARACTERISTICS VIN1 = VIN2 = VIN3 = AVIN = 5.0 V, TA = 25°C, unless otherwise noted. 4 SW VOUT1 2 VOUT1 2 VOUT2 3 EN VOUT3 1 4 09652-006 IIN 09652-003 3 CH4 2.0V/DIV 1MΩ BW 500M CH2 2.0V/DIV 1MΩ BW 20.0M CH3 2.0V/DIV 1MΩ BW 500M A CH2 1.88V CH1 CH2 CH3 CH4 200µs/DIV 1.0MS/s 1.0µs/pt Figure 3. 3-Channel Start-Up Waveforms 1MΩ BW 20.0M 1MΩ BW 500M 1MΩ BW 20.0M 1MΩ BW 500M A CH1 2.32V 50µs/DIV 2.0MS/s 500ns/pt Figure 6. Buck Startup, VOUT1 = 3.
PAGE 10
ADP5041 Data Sheet 1.24 3.90 –40°C +25°C +85°C 3.88 1.23 OUTPUT VOLTAGE (V) 3.84 3.82 3.80 3.78 3.76 3.74 0.1 1 OUTPUT CURRENT (A) 1.20 1.18 0.01 09652-009 3.70 0.01 1.21 1.19 –40°C +25°C +85°C 3.72 1.22 0.1 1 OUTPUT CURRENT (A) 09652-012 OUTPUT VOLTAGE (V) 3.86 Figure 12. Buck Load Regulation Across Temperature, VOUT1 = 1.2 V, Auto Mode Figure 9. Buck Load Regulation Across Temperature, VOUT1 = 3.8 V, Auto Mode 3.90 3.39 –40°C +25°C +85°C 3.37 –40°C +25°C +85°C 3.88 3.
PAGE 11
Data Sheet ADP5041 100 1.820 –40°C +25°C +85°C 1.815 90 VIN = 4.5V 80 VIN = 5.5V 70 EFFICIENCY (%) OUTPUT VOLTAGE (V) 1.810 1.805 1.800 1.795 60 50 40 30 1.790 20 1.785 0 0.001 09652-015 0.1 1 OUTPUT CURRENT (A) 0.1 1 OUTPUT CURRENT (A) Figure 18. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 3.8 V, PWM Mode Figure 15. Buck Load Regulation Across Temperature, VOUT1 = 1.8 V, PWM Mode 100 1.205 –40°C +25°C +85°C 90 80 1.200 VIN = 3.6V VIN = 4.5V VIN = 5.
PAGE 12
Data Sheet 100 100 90 90 80 80 70 70 EFFICIENCY (%) 60 50 40 60 50 40 30 30 10 0.001 0.01 0.1 1 OUTPUT CURRENT (A) 10 0 0.001 100 100 90 90 80 80 70 70 EFFICIENCY (%) EFFICIENCY (%) 1 Figure 24. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 1.2 V, PWM Mode 60 50 40 60 50 40 30 30 VIN = 2.4V VIN = 3.6V VIN = 4.5V VIN = 5.5V 10 0 0.001 0.01 0.1 20 1 OUTPUT CURRENT (A) –40°C +25°C +85°C 10 0 0.0001 09652-022 20 0.001 0.01 0.
PAGE 13
ADP5041 100 100 90 90 80 80 70 70 EFFICIENCY (%) 60 50 40 60 50 40 30 30 20 20 –40°C +25°C +85°C 0 0.0001 0.001 0.01 0.1 1 OUTPUT CURRENT (A) –40°C +25°C +85°C 10 0 0.001 09652-027 10 0.01 0.1 09652-030 EFFICIENCY (%) Data Sheet 1 OUTPUT CURRENT (A) Figure 27. Buck Efficiency vs. Load Current, Across Temperature, VIN = 5.0 V, VOUT1 = 1.8 V, Auto Mode Figure 30. Buck Efficiency vs. Load Current, Across Temperature, VIN = 5.0 V, VOUT1 = 1.2 V, PWM Mode 100 2.
PAGE 14
ADP5041 Data Sheet 2.0 VOUT VOUT = 1.2V 1.8 OUTPUT CURRENT (A) 1.6 4 1.4 1.2 ISW 2 1.0 0.8 0.6 SW 0.4 0.2 3.4 3.9 4.4 4.9 CH2 200mA/DIV 1MΩ BW 20.0M CH3 3.0V/DIV 1MΩ BW 20.0M 20.0M CH4 40.0mV/DIV 09652-033 2.9 5.4 VIN (V) Figure 33. Buck DC Current Capability vs. Input Voltage A CH1 640mV 5µs/DIV 500MS/s 2.0ns/pt 09652-036 3 0 2.4 Figure 36. Typical Waveforms, VOUT1 = 1.8 V, IOUT1 = 30 mA, Auto Mode 2.94 VOUT 2.92 FREQUENCY (MHz) 4 2.90 2.88 ISW 2 2.86 2.
PAGE 15
Data Sheet ADP5041 VOUT 4 VIN ISW VOUT 2 2 3 SW SW 1 A CH1 640mV 200ns/DIV 500MS/s 2.0ns/pt B 400M CH1 3.0V/DIV W B 20.0M CH2 30.0mV/DIV W B 1MΩ W 20.0M CH3 1.0V/DIV 09652-039 CH2 200mA/DIV 1MΩ BW 20.0M CH3 3.0V/DIV 1MΩ BW 20.0M 20.0M CH4 20.0mV/DIV Figure 39. Typical Waveforms, VOUT1 = 1.8 V, IOUT1 = 30 mA, PWM Mode A CH3 4.48V 200µs/DIV 1.0MS/s 1.0µs/pt 09652-042 3 Figure 42. Buck Response to Line Transient, Input Voltage from 4.5 V to 5.0 V, VOUT1 = 1.
PAGE 16
ADP5041 Data Sheet SW VIN 1 VOUT VOUT 2 3 2 SW IOUT 1 A CH3 4.48V 200µs/DIV 1.0MS/s 1.0µs/pt 1MΩ BW 20.0M CH1 4.0V/DIV B 20.0M CH2 100mV/DIV W CH3 300mA/DIV 1MΩ BW 20.0M 09652-045 B 400M CH1 3.0V/DIV W B 20.0M CH2 20.0mV/DIV W 1MΩ BW 20.0M CH3 1.0V/DIV Figure 45. Buck Response to Line Transient, Input Voltage from 4.5 V to 5.0 V, VOUT1 = 1.8 V, PWM Mode A CH3 150mA 500µs/DIV 20.0MS/s 50.0ns/pt 09652-048 3 Figure 48. Buck Response to Load Transient, IOUT1 = 50 mA to 500 mA, VOUT1 = 3.
PAGE 17
Data Sheet ADP5041 SW SW 1 1 VOUT VOUT 2 2 IOUT IOUT A CH3 94.0mA 200µs/DIV 500kS/s 2.0µs/pt 1MΩ BW 20.0M CH1 4.0V/DIV B 20.0M CH2 50.0mV/DIV W CH3 300mA/DIV 1MΩ BW 20.0M 09652-051 1MΩ BW 20.0M CH1 4.0V/DIV B 20.0M CH2 50.0mV/DIV W CH3 100mA/DIV 1MΩ BW 120M Figure 51. Buck Response to Load Transient, IOUT1 = 20 mA to 200 mA, VOUT1 = 1.2 V, Auto Mode A CH3 150mA 500µs/DIV 20.0MS/s 50.0ns/pt 09652-054 3 3 Figure 54. Buck Response to Load Transient, IOUT1 = 50 mA to 500 mA, VOUT1 = 3.
PAGE 18
ADP5041 Data Sheet 1 SW IIN VOUT 2 VOUT IOUT EN 94.0mA 200µs/DIV 500kS/s 2.0ns/pt CH1 2.0V/DIV CH2 2.0V/DIV CH3 200mA/DIV 09652-057 B 20.0M A CH3 CH1 4.0V/DIV W B 20.0M CH2 50.0mV/DIV W CH3 100mA/DIV 1MΩ BW 120.0M 1MΩ BW 20.0M A CH1 1MΩ BW 20.0M B 20.0M W 1.72V 50.0µs/DIV 200MS/s 5.0ns/pt 09652-060 3 Figure 60. LDO1, LDO2 Startup, VOUT = 3.3 V, IOUT = 5 mA Figure 57. Buck Response to Load Transient, IOUT1 = 20 mA to 200 mA, VOUT1 = 1.
PAGE 19
Data Sheet ADP5041 1.220 3.6V 4.5V 5.5V 2.8V 1.215 1.210 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 4.758 5.5V 4.708 4.658 1.205 1.200 1.195 1.190 5.0V 1.180 0.001 3.38 3.38 3.36 3.36 OUTPUT VOLTAGE (V) 3.40 3.34 5.5V 3.30 3.28 4.5V 3.6V 3.30 3.28 3.26 3.24 3.22 3.22 0.01 0.1 OUTPUT CURRENT (A) 3.20 0.001 0.1 Figure 67. LDO1, LDO2 Load Regulation Across Temperature, VIN = 3.6 V, VOUT = 3.3 V 1.800 1.800 3.6V 4.5V 5.5V 2.8V –40°C +25°C +85°C 1.795 OUTPUT VOLTAGE (V) 1.795 1.
PAGE 20
ADP5041 Data Sheet 1.820 1.220 –40°C +25°C +85°C 1.215 1.815 OUTPUT VOLTAGE (V) 1.210 OUTPUT VOLTAGE (V) 100µA 1mA 10mA 100mA 200mA 1.205 1.200 1.195 1.810 1.805 1.800 1.190 1.795 0.01 1.790 2.5 09652-069 1.180 0.001 0.1 OUTPUT CURRENT (A) 4.0 4.5 5.0 5.5 Figure 72. LDO1, LDO2 Line Regulation Across Input Voltage, VOUT = 1.8 V 1.201 4.75 100µA 1mA 10mA 100mA 200mA 100µA 1mA 10mA 100mA 200mA 1.200 1.199 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 3.5 INPUT VOLTAGE (V) Figure 69.
PAGE 21
Data Sheet ADP5041 200 180 VOUT GROUND CURRENT (µA) 160 2 140 120 100 80 20 0 3.8 4.3 4.8 3 09652-075 40 5.3 INPUT VOLTAGE (V) Figure 75. LDO1, LDO2 Ground Current vs. Input Voltage, Across Output Load (A), VOUT = 3.3 V IOUT CH2 30.0mV/DIV CH3 50.0mA/DIV B 20.0M A CH3 W 1MΩ BW 120M 42.0mA 200µs/DIV 500kS/s 2.0µs/pt 09652-078 0.000001A 0.0001A 0.001A 0.01A 0.1A 0.15A 0.3A 60 Figure 78. LDO1, LDO2 Response to Load Transient, IOUT from 1 mA to 80 mA, VOUT = 3.
PAGE 22
ADP5041 Data Sheet VIN 2 VOUT VOUT 2 3 IOUT B 20.0M A CH3 W 1MΩ BW 120M 89.6mA 200µs/DIV 500kS/s 2.0µs/pt B 20.0M A CH3 CH2 20.0mV/DIV W CH3 1.0V/DIV 1MΩ BW 20.0M 09652-081 CH2 50.0mV/DIV CH3 80.0mA/DIV Figure 81. LDO1, LDO2 Response to Load Transient, IOUT from 10 mA to 200 mA, VOUT = 1.8 V 4.84V 200µs/DIV 1.0MS/s 1.0µs/pt 09652-084 3 Figure 84. LDO1, LDO2 Response to Line Transient, Input Voltage from 4.5 V to 5.5 V, VOUT = 3.3 V VOUT VIN 2 VOUT 2 3 B 20.0M A CH3 CH2 30.
PAGE 23
Data Sheet ADP5041 RMS NOISE (µV) VIN VOUT 2 100 3 200µs/DIV 1.0MS/s 1.0µs/pt 10 0.0001 Figure 87. LDO1, LDO2 Response to Line Transient, Input Voltage from 3.3 V to 3.8 V, VOUT = 1.8 V VOUT 2 0.01 0.1 1 LOAD (mA) 10 100 1k Figure 90. LDO1 Output Noise vs. Load Current, Across Input and Output Voltage RMS NOISE (µV) VIN 0.001 09652-104 4.02V 09652-087 B 20.0M A CH3 CH2 20.0mV/DIV W CH3 1.0V/DIV 1MΩ BW 20.0M CH2; VOUT = 3.3V; VIN = 5V CH2; VOUT = 3.3V; VIN = 3.6V CH2; VOUT = 2.
PAGE 24
ADP5041 100 Data Sheet VOUT3 = 3.3V, VIN3 = 3.6V, VOUT3 = 1.5V, VIN3 = 1.8V, VOUT3 = 2.8V, VIN3 = 3.1V, –10 ILOAD = 300mA ILOAD = 300mA ILOAD = 300mA –20 –30 10 1mA 10mA 100mA 200mA 300mA PSRR (dB) NOISE (µV/√Hz) –40 1 –50 –60 –70 0.1 –80 10 100 1k 10k FREQUENCY (Hz) 100k 1M –100 10 Figure 93. LDO2 Noise Spectrum Across Output Voltage, VIN = VOUT + 0.
PAGE 25
Data Sheet ADP5041 –10 –10 –30 –20 –30 –40 PSRR (dB) –50 –60 –50 –60 –70 –70 –80 –80 –90 –90 100 1k 10k 100k FREQUENCY (Hz) 1M 10M –100 10 09652-113 PSRR (dB) –40 –100 10 1mA 10mA 100mA 200mA 300mA 100 1k 10k 100k FREQUENCY (Hz) 1M Figure 100. LDO1 PSRR Across Output Load, VIN2 = 1.8 V, VOUT2 = 1.5 V Figure 99. LDO1 PSRR Across Output Load, VIN2 = 5.0 V, VOUT2 = 1.5 V Rev.
PAGE 26
ADP5041 Data Sheet THEORY OF OPERATION VOUT1 FB1 WDI VTHR MR 85Ω ENWD ENBK AVIN VDDA WATCHDOG DETECTOR GM ERROR AMP PWM COMP VDDA SOFT START VIN1 52kΩ ILIMIT DEBOUNCE PSM COMP PWM/ PSM CONTROL BUCK1 LOW CURRENT nRSTO SW RESET GENERATOR VREF OSCILLATOR DRIVER AND ANTISHOOT THROUGH SYSTEM UNDERVOLTAGE LOCK OUT PGND MODE MODE EN1 ENABLE AND MODE CONTROL ENBK ENLDO1 EN2 EN3 600Ω ENLDO2 THERMAL SHUTDOWN SEL ENLDO2 LDO1 CONTROL VDDA VDDA LDO2 CONTROL OPMODE_FUSES 600Ω VIN2 FB2 AG
PAGE 27
Data Sheet ADP5041 Thermal Protection VOUT1 L1 – 1µH VIN1 In the event that the junction temperature rises above 150°C, the thermal shutdown circuit turns off the buck and the LDOs. Extreme junction temperatures can be the result of high current operation, poor circuit board design, or high ambient temperature.
PAGE 28
ADP5041 Data Sheet PSM Current Threshold The PSM current threshold is set to 100 mA. The buck employs a scheme that enables this current to remain accurately controlled, independent of input and output voltage levels. This scheme also ensures that there is very little hysteresis between the PSM current threshold for entry to, and exit from, the PSM mode. The PSM current threshold is optimized for excellent efficiency over all load currents.
PAGE 29
Data Sheet Manual Reset Input VTH VTH VOUT2 1V 0V VOUT2 nRSTO tRP tRD RSTO tRP 1V 0V 09652-093 0V tRD Figure 104. Reset Timing Diagram The ADP5041 has a reset threshold programming input pin, VTHR, to monitor a supply rail. The reset threshold voltage at VTHR input is typically 0.5 V. To monitor a voltage greater than 0.
PAGE 30
ADP5041 Data Sheet NO POWER APPLIED TO AVIN. ALL REGULATORS AND SUPERVISORY TURNED OFF NO POWER AVIN > VUVLO AVIN < VUVLO TRANSITION STATE POR INTERNAL CIRCUIT BIASED REGULATORS AND SUPERVISORY NOT ACTIVATED END OF POR STANDBY ENx = HIGH AVIN < VUVLO ALL ENx = LOW AVIN < VUVLO ALL REGULATORS AND SUPERVISORS ACTIVATED ACTIVE END OF RESET PULSE (tRP ) WDOG1 TIMEOUT (tWD) RESET NORMAL Figure 107. ADP5041 State Flow Rev.
PAGE 31
Data Sheet ADP5041 APPLICATIONS INFORMATION BUCK EXTERNAL COMPONENT SELECTION Trade-offs between performance parameters such as efficiency and transient response are made by varying the choice of external components in the applications circuit, as shown in Figure 1. Feedback Resistors Referring to Figure 102, the total combined resistance for R1 and R2 is not to exceed 400 kΩ. Inductor The high switching frequency of the ADP5041 buck allows for the selection of small chip inductors.
PAGE 32
ADP5041 Data Sheet Capacitors with lower equivalent series resistance (ESR) are preferred to guarantee low output voltage ripple, as shown in the following equation: ESRCOUT ≤ To minimize supply noise, place the input capacitor as close to the VIN pin of the buck as possible. As with the output capacitor, a low ESR capacitor is recommended. The effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 3 µF and a maximum of 10 µF.
PAGE 33
Data Sheet ADP5041 Table 13. Suggested 1.0 μF Capacitors Vendor Murata TDK Panasonic Taiyo Yuden Type X5R X5R X5R X5R Model GRM155B30J105K C1005JB0J105KT ECJ0EB0J105K LMK105BJ105MV-F Case Size 0402 0402 0402 0402 Voltage Rating (V) 6.3 6.3 6.3 10.0 Input and Output Capacitor Properties Use any good quality ceramic capacitor with the ADP5041 as long as it meets the minimum capacitance and maximum ESR requirements.
PAGE 34
ADP5041 Data Sheet Watchdog Software Considerations The efficiency for each regulator on the ADP5041 is given by In implementing the watchdog strobe code of the microprocessor, quickly switching WDI low to high and then high to low (minimizing WDI high time) is desirable for current consumption reasons. However, a more effective way of using the watchdog function can be considered. A low-to-high-to-low WDI pulse within a given subroutine prevents the watchdog from timing out.
PAGE 35
Data Sheet ADP5041 The inductor losses are estimated (without core losses) by PL ≅ I OUT1( RMS )2 × DCRL (4) where: DCRL is the inductor series resistance. IOUT1(RMS) is the rms load current of the buck regulator. I OUT1( RMS ) = I OUT1 × 1 + r/12 (5) where r is the normalized inductor ripple current. r ≈ VOUT1 × (1-D)/(IOUT1 × L × fSW) (6) where: L is inductance. fSW is switching frequency. D is duty cycle.
PAGE 36
ADP5041 Data Sheet affected by increasing the junction temperature. Additional information about product reliability can be found in the Analog Devices, Inc., Reliability Handbook, which is available at http://www.analog.com/reliability_handbook. The reliable operation of the buck regulator and the LDO regulator can be achieved only if the estimated die junction temperature of the ADP5041 (Equation 14) is less than 125°C.
PAGE 37
Data Sheet ADP5041 PCB LAYOUT GUIDELINES • Poor layout can affect ADP5041 performance, causing electromagnetic interference (EMI) and electromagnetic compatibility (EMC) problems, ground bounce, and voltage losses. Poor layout can also affect regulation and stability. A good layout is implemented using the following guidelines: • • SUGGESTED LAYOUT • Place the inductor, input capacitor, and output capacitor close to the IC using short tracks.
PAGE 38
ADP5041 Data Sheet BILL OF MATERIALS Table 14. Reference C1 C2, C3 C4 C5,C6 L1 IC1 Value 4.7 µF, X5R, 6.3 V 1 µF, X5R, 6.3 V 10 µF, X5R, 6.3 V 2.2 µF, X5R, 6.3 V 1 µH, 85 mΩ, 1400 mA 1 µH, 85 mΩ, 1350 mA 1 µH, 89 mΩ, 1800 mA 3-regulator micro PMU Part Number JMK107BJ475 LMK105BJ105MV-F JMK107BJ106MA-T JMK105BJ225MV-F LQM2MPN1R0NG0B MDT2520-CN XPL2010-1102ML ADP5041 Rev.
PAGE 39
Data Sheet ADP5041 FACTORY PROGRAMMABLE OPTIONS Table 15. Regulator Output Discharge Resistor Options Options Option 0 Option 1 Description All discharge resistors disabled All discharge resistors enabled Table 16. Undervoltage Lockout Options Options Option 0 Option 1 Min 1.95 3.10 Typ 2.15 3.65 Max 2.275 3.90 Unit V V Min 24 160 Typ 30 200 Max 36 240 Unit ms ms Typ 102 1.6 Max 122.4 1.92 Unit ms sec Table 17. Reset Timeout Options Options Option 0 Option 1 Table 18.
PAGE 40
ADP5041 Data Sheet OUTLINE DIMENSIONS PIN 1 INDICATOR 4.10 4.00 SQ 3.90 0.30 0.25 0.20 0.50 BSC 20 16 15 PIN 1 INDICATOR 1 EXPOSED PAD 2.65 2.50 SQ 2.35 5 11 0.80 0.75 0.70 0.50 0.40 0.30 6 10 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 0.25 MIN BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGD. 061609-B TOP VIEW Figure 115.