Datasheet

ADP5040 Data Sheet
Rev. 0 | Page 34 of 40
PCB LAYOUT GUIDELINES
Poor layout can affect ADP5040 performance, causing electro-
magnetic interference (EMI) and electromagnetic compatibility
(EMC) problems, ground bounce, and voltage losses. Poor
layout can also affect regulation and stability. A good layout is
implemented using the following guidelines:
• Place the inductor, input capacitor, and output capacitor
close to the IC using short tracks. These components carry
high switching frequencies, and large tracks act as antennas.
• Route the output voltage path away from the inductor and
SW node to minimize noise and magnetic interference.
• Maximize the size of ground metal on the component side
to help with thermal dissipation.
• Use a ground plane with several vias connecting to the
component side ground to further reduce noise interference
on sensitive circuit nodes.
SUGGESTED LAYOUT
See Figure 109 for an example layout.
GPL
NC
NC
NC
AGND
NC
2
GPL
GPL
GPL
GPL
VOUT3
VOUT1
VOUT2
PPL
PPL
PPL
Pin 1
GPL GPL
GPL GPL
GPL
GPL
PPL
PPL
TOP LAYER
09665-102
VIAS LEGEND:
PPL = POWER PLANE (+4V)
GPL = GROUND PLANE
2ND LAYER
MODE
EN
L1 – 1µH
0603
C5 – 4.7µF
10V/XR5 0603
C6 – 10µF
6.3V/XR5
0603
1.0
1.0
2.0
2.0
3.0
3.0
mm
mm
4.0
4.0
5.0
5.0
6.0
6.0
6.5
6.5 7.0
0.5
0.5
1.5
1.5
2.5
2.5
3.5
3.5
4.5
4.5
5.5
5.5
R
FILT
30Ω
0402
C3 – 1µF
10V/XR5
0402
C4– 2.2µF
6.3V/XR5
0402
EN3
VIN3
VOUT3
FB3
VOUT1
FB1
VIN2
VOUT2
FB2
C2 – 1µF
10V/XR5
0402
C5 – 2.2µF
6.3V/XR5
0402
AVIN
VIN
SW
PGND
EN1
ADP5040
Figure 109. Evaluation Board Layout