Datasheet

Data Sheet ADP5040
Rev. 0 | Page 33 of 40
Junction Temperature
In cases where the board temperature, T
A
, is known, the
thermal resistance parameter, θ
JA
, can be used to estimate the
junction temperature rise. T
J
is calculated from T
A
and P
D
using
the formula
T
J
= T
A
+ (P
D
× θ
JA
) (14)
The typical θ
JA
value for the 20-lead, 4 mm × 4 mm LFCSP is
38°C/W (see Table 6). A very important factor to consider is
that θ
JA
is based on a 4-layer, 4 inch × 3 inch, 2.5 oz copper, as
per JEDEC standard, and real applications may use different
sizes and layers. To remove heat from the device, it is important
to maximize the use of copper. Copper exposed to air dissipates
heat better than copper used in the inner layers. The exposed
pad (EP) should be connected to the ground plane with several
vias as shown in Figure 109.
If the case temperature can be measured, the junction temperature
is calculated by
T
J
= T
C
+ (P
D
× θ
JC
) (15)
where:
T
C
is the case temperature.
θ
JC
is the junction-to-case thermal resistance provided in Table 6.
When designing an application for a particular ambient
temperature range, calculate the expected ADP5040 power
dissipation (P
D
) due to the losses of all channels by using
Equation 8 to Equation 13. From this power calculation, the
junction temperature, T
J
, can be estimated using Equation 14.
The reliable operation of the buck regulator and the LDO
regulator can be achieved only if the estimated die junction
temperature of the ADP5040 (Equation 14) is less than 125°C.
Reliability and mean time between failures (MTBF) is highly
affected by increasing the junction temperature. Additional
information about product reliability can be found in the
Analog Devices, Inc., Reliability Handbook, which is available
at http://www.analog.com/reliability_handbook.
APPLICATION DIAGRAM
ON
OFF
FPWM
PWM/PSM
R
FILT
30Ω
SW
PGND
MODE
C4
10µF
L1
1µH
VIN1
EN3
EN1
VIN2
VIN3
EN2
AGND
VOUT2
VOUT1
FB3
VOUT3
C1
4.7µF
C2
1µF
C3
1µF
EN_BK
BUCK
EN_LDO1
LDO1
(DIGITAL)
EN_LDO2
LDO2
(ANALOG)
ON
OFF
ON
OFF
4
16
13
10
7
6
3
EP
1
14
FB2
FB1
15
17
9
11
8
12
R2
R1
2
R7
R8
C6
2.2µF
R4
R3
V
OUT1
AT
1.2A
C5
2.2µF
V
IN1
= 2.3V
TO 5.5V
V
IN2
= 1.7V
TO 5.5V
V
IN3
= 1.7V
TO 5.5V
V
OUT2
AT
300mA
V
OUT3
AT
300mA
09665-103
AVIN
Figure 108. Application Diagram