Micro PMU with 1.2 A Buck Regulator and Two 300 mA LDOs ADP5040 Data Sheet FEATURES GENERAL DESCRIPTION Input voltage range: 2.3 V to 5.5 V One 1.2 A buck regulator Two 300 mA LDOs 20-lead, 4 mm × 4 mm LFCSP package Overcurrent and thermal protection Soft start Undervoltage lockout Buck key specifications Output voltage range: 0.8 V to 3.
ADP5040 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Power Management Unit........................................................... 25 General Description ......................................................................... 1 Buck Section................................................................................ 26 Functional Block Diagram ..............................................................
Data Sheet ADP5040 SPECIFICATIONS GENERAL SPECIFICATIONS AVIN, VIN1 = 2.3 V to 5.5 V; AVIN, VIN1 ≥VIN2, VIN3; VIN2, VIN3 = 1.7 V to 5.5 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. Table 1.
ADP5040 Data Sheet Parameter SW CHARACTERISTICS SW On Resistance Symbol Test Conditions/Comments RPFET PFET, AVIN = VIN1 = 3.6 V PFET, AVIN = VIN1 = 5 V NFET, AVIN = VIN1 = 3.6 V NFET, AVIN = VIN1 = 5 V PFET switch peak current limit EN1 = 0 V RNFET Current Limit ACTIVE PULL-DOWN OSCILLATOR FREQUENCY 1 ILIMIT FOSC Min 1600 2.5 Typ Max Unit 180 140 170 150 1950 85 3.0 240 190 235 210 2300 mΩ mΩ mΩ mΩ mA Ω MHz 3.
Data Sheet ADP5040 Parameter Symbol Conditions POWER SUPPLY REJECTION RATIO PSRR 1 kHz, VIN2, VIN3 = 3.3 V, VOUT2, VOUT3 = 2.8 V, IOUT = 100 mA 100 kHz, VIN2, VIN3 = 3.3 V, VOUT2, VOUT3 = 2.8 V, IOUT = 100 mA 1 MHz, VIN2, VIN3 = 3.3 V, VOUT2, VOUT3 = 2.8 V, IOUT = 100 mA Min Typ Max Unit 66 dB 57 dB 60 dB All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
ADP5040 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 5. Parameter AVIN to AGND VIN1 to AVIN PGND to AGDN VIN2, VIN3, VOUTx, ENx, MODE, FBx, SW to AGND SW to PGND Storage Temperature Range Operating Junction Temperature Range Soldering Conditions ESD Human Body Model ESD Charged Device Model ESD Machine Model Rating −0.3 V to +6 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to (AVIN + 0.3 V) −0.3 V to (VIN1 + 0.
Data Sheet ADP5040 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADP5040 20 19 18 17 16 NC NC NC MODE EN2 TOP VIEW (Not to Scale) 15 14 13 12 11 1 2 3 4 5 FB2 VOUT2 VIN2 FB1 VOUT1 NOTES 1. EXPOSED PAD MUST BE CONNECTED TO SYSTEM GROUND PLANE. 09665-002 AVIN 6 VIN1 7 SW 8 PGND 9 EN1 10 FB3 VOUT3 VIN3 EN3 NC Figure 2. Pin Configuration—View from Top of the Die Table 7. Preliminary Pin Function Descriptions Pin No.
ADP5040 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VIN1 = VIN2 = VIN3 = AVIN = 5.0 V, TA = 25°C, unless otherwise noted. 4 SW VOUT1 2 VOUT1 2 VOUT2 3 EN VOUT3 1 4 IIN A CH2 1.88V 200µs/DIV 1.0MS/s 1.0µs/pt CH1 CH2 CH3 CH4 09665-003 CH4 2.0V/DIV 1MΩ BW 500M CH2 2.0V/DIV 1MΩ BW 20.0M CH3 2.0V/DIV 1MΩ BW 500M Figure 3. 3-Channel Start-Up Waveforms 1MΩ BW 20.0M 1MΩ BW 500M 1MΩ BW 20.0M 1MΩ BW 500M A CH1 2.32V 50µs/DIV 2.0MS/s 500ns/pt Figure 6. Buck Startup, VOUT1 = 3.
Data Sheet ADP5040 1.24 3.90 –40°C +25°C +85°C 3.88 1.23 OUTPUT VOLTAGE (V) 3.84 3.82 3.80 3.78 3.76 3.74 0.1 1 OUTPUT CURRENT (A) 1.20 1.18 0.01 09665-009 3.70 0.01 1.21 1.19 –40°C +25°C +85°C 3.72 1.22 0.1 1 OUTPUT CURRENT (A) 09665-012 OUTPUT VOLTAGE (V) 3.86 Figure 12. Buck Load Regulation Across Temperature, VOUT1 = 1.2 V, Auto Mode Figure 9. Buck Load Regulation Across Temperature, VOUT1 = 3.8 V, Auto Mode 3.90 3.39 –40°C +25°C +85°C 3.37 –40°C +25°C +85°C 3.88 3.
ADP5040 Data Sheet 1.820 100 –40°C +25°C +85°C 1.815 90 VIN = 4.5V 80 VIN = 5.5V 70 EFFICIENCY (%) OUTPUT VOLTAGE (V) 1.810 1.805 1.800 1.795 60 50 40 30 1.790 20 1.785 0 0.001 09665-015 0.1 1 OUTPUT CURRENT (A) 0.1 1 OUTPUT CURRENT (A) Figure 15. Buck Load Regulation Across Temperature, VOUT1 = 1.8 V, PWM Mode Figure 18. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 3.8 V, PWM Mode 1.205 100 –40°C +25°C +85°C 90 80 1.200 VIN = 3.6V VIN = 4.5V VIN = 5.
ADP5040 100 100 90 90 80 80 70 70 EFFICIENCY (%) 60 50 40 60 50 40 30 30 10 0.001 0.01 0.1 1 OUTPUT CURRENT (A) 10 0 0.001 100 100 90 90 80 80 70 70 EFFICIENCY (%) EFFICIENCY (%) 1 Figure 24. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 1.2 V, PWM Mode 60 50 40 60 50 40 30 30 VIN = 2.4V VIN = 3.6V VIN = 4.5V VIN = 5.5V 10 0 0.001 0.01 0.1 20 1 OUTPUT CURRENT (A) –40°C +25°C +85°C 10 0 0.0001 09665-022 20 0.001 0.01 0.
Data Sheet 100 100 90 90 80 80 70 70 EFFICIENCY (%) 60 50 40 60 50 40 30 30 20 20 –40°C +25°C +85°C 0 0.0001 0.001 0.01 0.1 1 OUTPUT CURRENT (A) –40°C +25°C +85°C 10 0 0.001 09665-027 10 0.01 0.1 09665-030 EFFICIENCY (%) ADP5040 1 OUTPUT CURRENT (A) Figure 27. Buck Efficiency vs. Load Current, Across Temperature, VIN = 5.0 V, VOUT1 = 1.8 V, Auto Mode Figure 30. Buck Efficiency vs. Load Current, Across Temperature, VIN = 5.0 V, VOUT1 = 1.2 V, PWM Mode 100 2.
Data Sheet ADP5040 2.0 VOUT VOUT = 1.2V 1.8 OUTPUT CURRENT (A) 1.6 4 1.4 1.2 ISW 2 1.0 0.8 0.6 SW 0.4 0.2 3.4 3.9 4.4 4.9 CH2 200mA/DIV 1MΩ BW 20.0M CH3 3.0V/DIV 1MΩ BW 20.0M 20.0M CH4 40.0mV/DIV 09665-033 2.9 5.4 VIN (V) Figure 33. Buck DC Current Capability vs. Input Voltage A CH1 640mV 5µs/DIV 500MS/s 2.0ns/pt 09665-036 3 0 2.4 Figure 36. Typical Waveforms, VOUT1 = 1.8 V, IOUT1 = 30 mA, Auto Mode 2.94 VOUT 2.92 FREQUENCY (MHz) 4 2.90 ISW 2.88 2 2.86 2.
ADP5040 Data Sheet VOUT 4 VIN VOUT ISW 2 2 3 SW SW 1 A CH1 640mV 200ns/DIV 500MS/s 2.0ns/pt B 400M CH1 3.0V/DIV W B 20.0M CH2 30.0mV/DIV W B 1MΩ W 20.0M CH3 1.0V/DIV 09665-039 CH2 200mA/DIV 1MΩ BW 20.0M CH3 3.0V/DIV 1MΩ BW 20.0M 20.0M CH4 20.0mV/DIV Figure 39. Typical Waveforms, VOUT1 = 1.8 V, IOUT1 = 30 mA, PWM Mode A CH3 4.48V 200µs/DIV 1.0MS/s 1.0µs/pt 09665-042 3 Figure 42. Buck Response to Line Transient, Input Voltage from 4.5 V to 5.0 V, VOUT1 = 1.
Data Sheet ADP5040 SW VIN 1 VOUT VOUT 2 3 2 SW IOUT 1 A CH3 4.48V 200µs/DIV 1.0MS/s 1.0µs/pt 1MΩ BW 20.0M CH1 4.0V/DIV B 20.0M CH2 100mV/DIV W CH3 300mA/DIV 1MΩ BW 20.0M 09665-045 B 400M CH1 3.0V/DIV W B 20.0M CH2 20.0mV/DIV W B 1MΩ W 20.0M CH3 1.0V/DIV Figure 45. Buck Response to Line Transient, Input Voltage from 4.5 V to 5.0 V, VOUT1 = 1.8 V, PWM Mode A CH3 150mA 500µs/DIV 20.0MS/s 50.0ns/pt 09665-048 3 Figure 48. Buck Response to Load Transient, IOUT1 = 50 mA to 500 mA, VOUT1 = 3.
ADP5040 Data Sheet SW SW 1 1 VOUT VOUT 2 2 IOUT IOUT A CH3 94.0mA 200µs/DIV 500kS/s 2.0µs/pt 1MΩ BW 20.0M CH1 4.0V/DIV B 20.0M CH2 50.0mV/DIV W CH3 300mA/DIV 1MΩ BW 20.0M 09665-051 1MΩ BW 20.0M CH1 4.0V/DIV B 20.0M CH2 50.0mV/DIV W CH3 100mA/DIV 1MΩ BW 120M Figure 51. Buck Response to Load Transient, IOUT1 = 20 mA to 200 mA, VOUT1 = 1.2 V, Auto Mode A CH3 150mA 500µs/DIV 20.0MS/s 50.0ns/pt 09665-054 3 3 Figure 54. Buck Response to Load Transient, IOUT1 = 50 mA to 500 mA, VOUT1 = 3.
Data Sheet ADP5040 1 SW IIN VOUT 2 VOUT IOUT 94.0mA 200µs/DIV 500kS/s 2.0ns/pt CH1 2.0V/DIV CH2 2.0V/DIV CH3 200mA/DIV 09665-057 B 20.0M A CH3 CH1 4.0V/DIV W B 20.0M CH2 50.0mV/DIV W B CH3 100mA/DIV 1MΩ W 120.0M Figure 57. Buck Response to Load Transient, IOUT1 = 20 mA to 200 mA, VOUT1 = 1.2 V, PWM Mode 1MΩ BW 20.0M A CH1 1MΩ BW 20.0M B 20.0M W 1.72V 50.0µs/DIV 200MS/s 5.0ns/pt 09665-060 EN 3 Figure 60. LDO1, LDO2 Startup, VOUT = 3.
ADP5040 Data Sheet 1.220 3.6V 4.5V 5.5V 2.8V 1.215 1.210 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 4.758 5.5V 4.708 4.658 1.205 1.200 1.195 1.190 5.0V 0.1 OUTPUT CURRENT (A) 1.180 0.001 3.40 3.38 3.38 3.36 3.36 OUTPUT VOLTAGE (V) 3.34 5.5V 3.30 3.28 4.5V 3.6V 3.34 3.32 3.30 3.28 3.26 3.22 3.20 0.001 0.01 09665-064 3.22 3.20 0.001 0.1 OUTPUT CURRENT (A) 0.1 OUTPUT CURRENT (A) Figure 64. LDO1, LDO2 Load Regulation Across Input Voltage, VOUT = 3.3 V Figure 67.
Data Sheet ADP5040 1.820 1.220 –40°C +25°C +85°C 1.215 OUTPUT VOLTAGE (V) 1.210 OUTPUT VOLTAGE (V) 100µA 1mA 10mA 100mA 200mA 1.815 1.205 1.200 1.195 1.810 1.805 1.800 1.190 1.795 0.01 1.790 2.5 09665-069 1.180 0.001 0.1 OUTPUT CURRENT (A) 4.0 4.5 5.0 5.5 Figure 72. LDO1, LDO2 Line Regulation Across Input Voltage, VOUT = 1.8 V 1.201 4.75 100µA 1mA 10mA 100mA 200mA 100µA 1mA 10mA 100mA 200mA 1.200 1.199 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 3.5 INPUT VOLTAGE (V) Figure 69.
ADP5040 Data Sheet 200 180 VOUT GROUND CURRENT (µA) 160 2 140 120 100 80 20 0 3.8 4.3 4.8 3 09665-075 40 5.3 INPUT VOLTAGE (V) Figure 75. LDO1, LDO2 Ground Current vs. Input Voltage, Across Output Load (A), VOUT = 3.3 V IOUT CH2 30.0mV/DIV CH3 50.0mA/DIV B 20.0M A CH3 W 1MΩ BW 120M 42.0mA 200µs/DIV 500kS/s 2.0µs/pt 09665-078 0.000001A 0.0001A 0.001A 0.01A 0.1A 0.15A 0.3A 60 Figure 78. LDO1, LDO2 Response to Load Transient, IOUT from 1 mA to 80 mA, VOUT = 3.
Data Sheet ADP5040 VIN 2 VOUT VOUT 2 3 IOUT B 20.0M A CH3 W 1MΩ BW 120M 89.6mA 200µs/DIV 500kS/s 2.0µs/pt B 20.0M A CH3 CH2 20.0mV/DIV W CH3 1.0V/DIV 1MΩ BW 20.0M 09665-081 CH2 50.0mV/DIV CH3 80.0mA/DIV Figure 81. LDO1, LDO2 Response to Load Transient, IOUT from 10 mA to 200 mA, VOUT = 1.8 V 4.84V 200µs/DIV 1.0MS/s 1.0µs/pt 09665-084 3 Figure 84. LDO1, LDO2 Response to Line Transient, Input Voltage from 4.5 V to 5.5 V, VOUT = 3.3 V VOUT VIN 2 VOUT 2 3 B 20.0M A CH3 CH2 30.
ADP5040 Data Sheet RMS NOISE (µV) VIN VOUT 2 100 3 200µs/DIV 1.0MS/s 1.0µs/pt 10 0.0001 Figure 87. LDO1, LDO2 Response to Line Transient, Input Voltage from 3.3 V to 3.8 V, VOUT = 1.8 V VOUT 2 0.01 0.1 1 LOAD (mA) 10 100 1k Figure 90. LDO1 Output Noise vs. Load Current, Across Input and Output Voltage RMS NOISE (µV) VIN 0.001 09665-104 4.02V 09665-087 B 20.0M A CH3 CH2 20.0mV/DIV W CH3 1.0V/DIV 1MΩ BW 20.0M CH2; VOUT = 3.3V; VIN = 5V CH2; VOUT = 3.3V; VIN = 3.6V CH2; VOUT = 2.
Data Sheet 100 ADP5040 VOUT3 = 3.3V, VIN3 = 3.6V, VOUT3 = 1.5V, VIN3 = 1.8V, VOUT3 = 2.8V, VIN3 = 3.1V, –10 ILOAD = 300mA ILOAD = 300mA ILOAD = 300mA –20 –30 –40 PSRR (dB) NOISE (µV/√Hz) 10 1mA 10mA 100mA 200mA 300mA 1 –50 –60 –70 0.1 –80 10 100 1k 10k FREQUENCY (Hz) 100k 1M –100 10 Figure 93. LDO2 Noise Spectrum Across Output Voltage, VIN = VOUT + 0.
ADP5040 Data Sheet –10 –10 –30 –20 –30 –40 PSRR (dB) –50 –60 –50 –60 –70 –70 –80 –80 –90 –90 100 1k 10k 100k FREQUENCY (Hz) 1M 10M –100 10 09665-113 PSRR (dB) –40 –100 10 1mA 10mA 100mA 200mA 300mA 100 1k 10k 100k FREQUENCY (Hz) 1M Figure 100. LDO1 PSRR Across Output Load, VIN2 = 1.8 V, VOUT2 = 1.5 V Figure 99. LDO1 PSRR Across Output Load, VIN2 = 5.0 V, VOUT2 = 1.5 V Rev.
Data Sheet ADP5040 THEORY OF OPERATION VOUT1 FB1 85Ω ENBK AVIN VDDA GM ERROR AMP ENBK MODE ENLDO1 PWM COMP SOFT START VIN1 EN1 ENABLE & MODE CONTROL ENLDO2 EN2 MODE EN3 SEL PSM COMP ILIMIT LOW CURRENT OPMODE_FUSES PWM/ PSM CONTROL BUCK1 SW OSCILLATOR DRIVER AND ANTISHOOT THROUGH SYSTEM UNDERVOLTAGE LOCK OUT PGND 600Ω ENLDO2 THERMAL SHUTDOWN AGND LDO1 CONTROL VDDA VDDA LDO2 CONTROL 600Ω VIN2 FB2 VOUT2 VIN3 FB3 VOUT3 09665-090 ENLDO1 ADP5040 Figure 101.
ADP5040 Data Sheet Thermal Protection VOUT1 VIN1 In the event that the junction temperature rises above 150°C, the thermal shutdown circuit turns off the buck and the LDOs. Extreme junction temperatures can be the result of high current operation, poor circuit board design, or high ambient temperature. A 20°C hysteresis is included in the thermal shutdown circuit so that when thermal shutdown occurs, the buck and the LDOs do not return to normal operation until the on-chip temperature drops below 130°C.
Data Sheet ADP5040 The ADP5040 has a dedicated MODE pin controlling the PSM and PWM operation. A high logic level applied to the MODE pin forces the buck to operate in PWM mode. A logic level low sets the buck to operate in auto PSM/PWM. PSM Current Threshold The PSM current threshold is set to 100 mA. The buck employs a scheme that enables this current to remain accurately controlled, independent of input and output voltage levels.
ADP5040 Data Sheet NO POWER APPLIED TO AVIN. ALL REGULATORS TURNED OFF NO POWER AVIN > VUVLO AVIN < VUVLO POR INTERNAL CIRCUIT BIASED REGULATORS NOT ACTIVATED END OF POR STANDBY AVIN < VUVLO ALL ENx = LOW ENx = HIGH ACTIVE ALL REGULATORS ACTIVATED Figure 104. ADP5040 State Flow Rev.
Data Sheet ADP5040 APPLICATIONS INFORMATION BUCK EXTERNAL COMPONENT SELECTION Trade-offs between performance parameters such as efficiency and transient response are made by varying the choice of external components in the applications circuit, as shown in Figure 1. Feedback Resistors Referring to Figure 102, the total combined resistance for R1 and R2 is not to exceed 400 kΩ. Inductor The high switching frequency of the ADP5040 buck allows for the selection of small chip inductors.
ADP5040 Data Sheet Capacitors with lower equivalent series resistance (ESR) are preferred to guarantee low output voltage ripple, as shown in the following equation: ESRCOUT ≤ To minimize supply noise, place the input capacitor as close to the VIN pin of the buck as possible. As with the output capacitor, a low ESR capacitor is recommended. The effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 3 µF and a maximum of 10 µF.
Data Sheet ADP5040 Table 12. Suggested 1.0 μF Capacitors Vendor Murata TDK Panasonic Taiyo Yuden Type X5R X5R X5R X5R Model GRM155R61A105ME15 C1005JB0J105KT ECJ0EB0J105K LMK105BJ105MV-F Case Size 0402 0402 0402 0402 Voltage Rating (V) 10.0 6.3 6.3 10.0 Input and Output Capacitor Properties Use any good quality ceramic capacitor with the ADP5040 as long as it meets the minimum capacitance and maximum ESR requirements.
ADP5040 Data Sheet to derive the power lost in the inductor, and then calculate the power dissipation in the buck converter using Equation 3. Add the power dissipated in the buck and in the LDOs to find the total dissipated power. Note that the buck efficiency curves are typical values and may not be provided for all possible combinations of VIN, VOUT, and IOUT. To account for these variations, it is necessary to include a safety margin when calculating the power dissipated in the buck.
Data Sheet ADP5040 Junction Temperature If the case temperature can be measured, the junction temperature is calculated by In cases where the board temperature, TA, is known, the thermal resistance parameter, θJA, can be used to estimate the junction temperature rise. TJ is calculated from TA and PD using the formula TJ = TA + (PD × θJA) TJ = TC + (PD × θJC) (15) where: TC is the case temperature. θJC is the junction-to-case thermal resistance provided in Table 6.
ADP5040 Data Sheet PCB LAYOUT GUIDELINES Poor layout can affect ADP5040 performance, causing electromagnetic interference (EMI) and electromagnetic compatibility (EMC) problems, ground bounce, and voltage losses. Poor layout can also affect regulation and stability. A good layout is implemented using the following guidelines: • • SUGGESTED LAYOUT • Place the inductor, input capacitor, and output capacitor close to the IC using short tracks.
Data Sheet ADP5040 BILL OF MATERIALS Table 13. Reference C1 C2, C3 C4 C5, C6 L1 IC1 Value 4.7 µF, X5R, 6.3 V 1 µF, X5R, 6.3 V 10 µF, X5R, 6.3 V 2.2 µF, X5R, 6.3 V 1 µH, 85 mΩ, 1400 mA 1 µH, 85 mΩ, 1350 mA 1 µH, 89 mΩ, 1800 mA 3-regulator micro PMU Part Number JMK107BJ475 LMK105BJ105MV-F JMK107BJ106MA-T JMK105BJ225MV-F LQM2MPN1R0NG0B MDT2520-CN XPL2010-1102ML ADP5040 Rev.
ADP5040 Data Sheet FACTORY PROGRAMMABLE OPTIONS Table 14. Regulator Output Discharge Resistor Options Selection 0 1 All discharge resistors disabled All discharge resistors enabled Table 15. Under Voltage Lockout options Selection 0 1 Min 1.95 3.10 Typ 2.15 3.65 Rev. 0 | Page 36 of 40 Max 2.275 3.
Data Sheet ADP5040 OUTLINE DIMENSIONS PIN 1 INDICATOR 4.10 4.00 SQ 3.90 0.30 0.25 0.20 0.50 BSC 20 16 15 PIN 1 INDICATOR 1 EXPOSED PAD 2.65 2.50 SQ 2.35 5 11 0.80 0.75 0.70 0.50 0.40 0.30 10 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 6 0.25 MIN BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGD. 061609-B TOP VIEW Figure 110.
ADP5040 Data Sheet NOTES Rev.
Data Sheet ADP5040 NOTES Rev.
ADP5040 Data Sheet NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D096665-0-12/11(0) Rev.
