Datasheet

ADP5037 Data Sheet
Rev. D | Page 24 of 28
PCB LAYOUT GUIDELINES
Poor layout can affect ADP5037 performance, causing electro-
magnetic interference (EMI) and electromagnetic compatibility
(EMC) problems, ground bounce, and voltage losses. Poor layout
can also affect regulation and stability. A good layout is
implemented using the following guidelines.
• Place the inductor, input capacitor, and output capacitor
close to the IC using short tracks. These components carry
high switching frequencies, and large tracks act as antennas.
• Route the output voltage path away from the inductor and
SW node to minimize noise and magnetic interference.
• Maximize the size of ground metal on the component side
to help with thermal dissipation.
• Use a ground plane with several vias connecting to the
component side ground to further reduce noise interference
on sensitive circuit nodes.
• Connect VIN1, VIN2, and AVIN together close to the IC
using short tracks.
In addition, refer to the UG-271 User Guide.