Datasheet

ADP5037 Data Sheet
Rev. D | Page 12 of 28
4
2
T
1
CH1
50.0mV
B
W
CH4 5.00V
B
W
M 20.0µs
A CH2 408mA
T
20.40%
CH2 200mA Ω
B
W
VOUT
I
OUT
SW
09887-045
Figure 27. BUCK1 Response to Load Transient, I
OUT1
from 20 mA to 180 mA,
V
OUT1
= 3.3 V, Auto Mode
4
2
T
1
CH1 100mV
B
W
CH4 5.00V
B
W
M 20.0µs A CH2 88.0mA
T 19.20%
CH2 200mA Ω
B
W
VOUT
I
OUT
SW
09887-046
Figure 28. BUCK2 Response to Load Transient, I
OUT2
from 20 mA to 180 mA,
V
OUT2
= 1.8 V, Auto Mode
4
1
3
T
2
CH1 5.00V
B
W
CH4 5.00V
B
W
M 400ns A CH4 1.90V
T
50.00%
CH2 5.00V
B
W
CH3 5.00V
B
W
VOUT1
VOUT2
SW1
SW2
09887-060
Figure 29. VOUT and SW Waveforms for BUCK1 and BUCK2 in PWM Mode
Showing Out-of-Phase Operation
CH1 100mA
CH3 1.00V
CH2 5.0V M40.0µs 2.5GS/s A CH2 4.20V
2
3
1
T 159.4µs
EN
VOUT
I
IN
09887-109
Figure 30. LDO Startup, V
OUT3
= 1.8 V
3.304
3.303
3.302
3.301
3.300
3.299
3.298
3.297
3.296
3.295
3.294
0
0.1 0.2 0.3
V
OUT
(V)
I
OUT
(A)
V
IN
= 3.8V
V
IN
= 4.2V
V
IN
= 5.5V
09887-110
Figure 31. LDO Load Regulation Across Input Voltage, V
OUT3
= 3.3 V
0
50
100
150
200
250
300
350
400
2.3 2.8 3.3 3.8 4.3 4.8 5.3
RD
S
ON
(mΩ)
INPUT VOLTAGE (V)
+25°C
+125°C
–40°C
09887-037
Figure 32. NMOS RDS
ON
vs. Input Voltage Across Temperature