Datasheet

ADP5023 Data Sheet
Rev. D | Page 16 of 28
operation, poor circuit board design, or high ambient
temperature. A 20°C hysteresis is included so that when thermal
shutdown occurs, the regulators do not return to operation until
the on-chip temperature drops below 130°C. When coming out
of thermal shutdown, all regulators restart with soft-start
control.
Undervoltage Lockout
To protect against battery discharge, undervoltage lockout
(UVLO) circuitry is integrated into the system. If the input
voltage on AVIN drops below a typical 2.15 V UVLO threshold,
all channels shut down. In the buck channels, both the power
switch and the synchronous rectifier turn off. When the voltage
on AVIN rises above the UVLO threshold, the part is enabled
once more.
Alternatively, the user can select device models with a UVLO
set at a higher level, suitable for 5 V supply applications. For
these models, the device reaches the turn-off threshold when
the input supply drops to 3.65 V typical.
In case of a thermal or UVLO event, the active pull-downs (if
factory enabled) are enabled to discharge the output capacitors
quickly. The pull-down resistors remain engaged until the thermal
fault event is no longer present, or the input supply voltage falls
below the V
POR
voltage level. The typical value of V
POR
is approx-
imately 1 V.
Enable/Shutdown
The ADP5023 has an individual control pin for each regulator.
A logic level high applied to the ENx pin activates a regulator,
whereas a logic level low turns off a regulator.
Figure 46 shows the regulator activation timings for the
ADP5023 when all enable pins are connected to AVIN. Also
shown is the active pull-down activation.
AVIN
VOUT3
VOUT1
VUVLO
VOUT2
VPOR
BUCK2
PULL-DOWN
BUCK1, LDO1
PULL-DOWNS
50µs (MIN)
30µs (MIN)
50µs (MIN)
30µs (MIN)
09889-148
Figure 46. Regulator Sequencing on ADP5023 (
EN1 = EN2 = EN3 = V
AVIN
)