Datasheet

ADP5023 Data Sheet
Rev. D | Page 12 of 28
4
2
T
1
CH1 50.0mV
CH4 5.00V
M 20.0µs
A CH2 408mA
T 20.40%
CH2 200m
A Ω
VOUT
I
OUT
SW
09889-017
Figure 27. BUCK1 Response to Load Transient, I
OUT1
= 20 mA to 180 mA,
V
OUT1
= 3.3 V, Auto Mode
4
2
T
1
CH1 100mV
CH4 5.00V
M 20.0µs A CH2 88.0mA
T 19.20%
CH2 200m
A Ω
VOUT
I
OUT
SW
09889-018
Figure 28. BUCK2 Response to Load Transient, I
OUT2
= 20 mA to 180 mA,
V
OUT2
= 1.8 V, Auto Mode
4
1
3
T
2
CH1 5.00V
CH4 5.00V
M 400ns A CH4 1.90V
T 50.00%
CH2 5.00V
CH3 5.00V
VOUT1
VOUT2
SW1
SW2
09889-066
Figure 29. VOUT and SW Waveforms for BUCK1 and BUCK2 in PWM Mode
Showing Out-of-Phase Operation
2
3
1
2.5GS/s
1M points
A CH2 4.20V
VOUT
EN
I
IN
09889-022
CH1 100mA
CH2 5.00V
CH3 1.00V
T 159.400
µ
s
M40.0µs
Figure 30. LDO Startup, V
OUT3
= 1.8 V
3.304
3.294
0 0.3
V
OUT
(V)
I
OUT
(A)
0.1 0.2
V
IN
= 5.5V
3.295
3.296
3.297
3.298
3.299
3.300
3.301
3.302
3.303
V
IN
= 4.2V
V
IN
= 3.8V
09889-046
Figure 31. LDO Load Regulation Across Input Voltage, V
OUT3
= 3.3 V
0
50
100
150
200
250
300
350
400
2.3 2.8 3.3 3.8 4.3 4.8 5.3
RDS
ON
(mΩ)
INPUT VOLTAGE (V)
09703-037
+25°C
+125°C
–40°C
Figure 32. NMOS RDS
ON
vs. Input Voltage Across Temperature