Datasheet

ADP5022
Rev. C | Page 23 of 28
EVALUATION BOARD SCHEMATICS AND ARTWORK
A1
D4
D3
C4
D1
D2
C1
VIN1
VIN2
VDDA
SW1
B1
B4
R1
0Ω
R2
0Ω
A4
A3
A2
C3
B2
B3
C2
VOUT1
PGND1
SW2
VOUT2
PGND2
VOUT3
VIN3
AGND
MODE
EN1
EN2
C
OUT
_2
0603
10µF
C3
0603
4.7µF
C1
0402
1µF
C2
0603
4.7µF
C
OUT
_3
0402
1µF
EN3
LDO
J8
J9
J10
J13
J12
J11
BUCK2
L1
1µH
L2
1µH
BUCK1
C
OUT
_1
0603
10µF
J1
J2
J3
J4
J5
J7
J6
08253-007
Figure 52. Evaluation Board Schematic
SUGGESTED LAYOUT
0
8253-008
Figure 53. Top Layer, Recommended Layout
08253-009
Figure 54. Second Layer, Recommended Layout