Datasheet

ADP5020
Rev. 0 | Page 9 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
15VOUT1
14VOUT1
13VDD3
12VOUT3
11EN/GPIO
3 VDDA
2VOUT2
1 PGND2
4AGND
5SYNC
10
XSHTDN
9
VDD_IO
8
SCL
6
D
GND
7
SDA
18
VDD1
17
SW
1
16
PGND1
19
VDD2
20
SW
2
BOTTOM VIEW
(Not to Scale)
EXPOSED PAD
ADP5020
07774-004
NOTES
1. EXPOSED PAD SHOULD BE CONNECTED
TO PGND1 AND PGND2.
Figure 4. Pin Configuration (Bottom View)
VOUT1
VOUT1
VDD3
VOUT3
EN/GPIO
VDDA
VOUT2
PGND2
AGND
SYNC
PIN 1
INDICATOR
1
2
3
4
5
13
14
15
12
11
6
DGND
7
SDA
8
SCL
10
XSHTDN
9
VDD_IO
18
VDD1
19
VDD2
20
SW
2
17
SW
1
16
PGND1
TOP VIEW
(Not to Scale)
ADP5020
07774-005
Figure 5. Pin Configuration (Top View)
Table 9. Pin Function Descriptions
Pin No. Mnemonic Description
1 PGND2 Power Ground Buck 2.
2 VOUT2 Feedback Buck 2.
3 VDDA Supply Voltage Internal Analog Circuit.
4 AGND Analog Ground.
5 SYNC
Frequency Synchronization. Connect to an external 19.2 MHz or 9.6 MHz clock signal to synchronize the
internal oscillator.
6 DGND Digital Ground.
7 SDA I
2
C Data.
8 SCL I
2
C Clock.
9 VDD_IO Supply Voltage for Internal Logic Inputs/Outputs.
10 XSHTDN Shutdown Output, Active Low.
11 EN/GPIO
After power-on reset, this pin is defined as enable (EN). To enable active high, the I
2
C command can program
this pin to be an output (GPIO). A weak pull-down resistor is enabled when the pin operates as EN.
12 VOUT3 Regulated Output Voltage from LDO.
13 VDD3 Supply Voltage LDO.
14, 15 VOUT1 Feedback/Driver Buck 1 Output.
16 PGND1 Power Ground Buck 1.
17 SW1 Switch Pin Buck 1.
18 VDD1 Supply Voltage Buck 1.
19 VDD2 Supply Voltage Buck 2.
20 SW2 Switch Pin Buck 2.
EPAD Exposed paddle Exposed pad should be connected to PGND1 and PGND2.