Datasheet

ADP5020
Rev. 0 | Page 8 of 28
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter Rating
VDD1, VDD2, VDD3 −0.3 V to +6 V
SW1, SW2 −0.3 V to +6 V
VOUT1, VOUT2, VOUT3 −0.3 V to +6 V
VDD_IO −0.3V to +3.6 V
EN, SCL, SDA, SYNC, XSHTDN −0.3 V to V
DD_IO
+ 0.3 V
Operating Temperature Range
Ambient −40°C to +85°C
Junction −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Lead Temperature 260°C
Soldering (10 sec) 260°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
V
ESD
Machine Model Range −200 V to +200 V
Human Body Model Range −2000 V to +2000 V
Charged Device Model ±750 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
The ADP5020 can be damaged when the junction temperature
(T
J
) limits are exceeded. Monitoring the ambient temperature
does not guarantee that T
J
is within the specified temperature
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
have to be derated. In applications having moderate power dis-
sipation and low PCB thermal resistance, the maximum ambient
temperature can exceed the maximum limit as long as the junction
temperature is within specification limits. The T
J
of the device is
dependent on the ambient temperature (T
A
), the power dissipation
(PD) of the device, and the junction-to-ambient thermal resistance
of the package (θ
JA
). Maximum T
J
is calculated from T
A
and PD
using the following formula:
T
J
= T
A
+ (PD × θ
JA
)
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 8. Thermal Resistance
Package Type θ
JA
θ
JC
Unit
20-Lead LFCSP (CP-20-4) 47.4 4.3 °C/W
Thermal Data
Junction-to-ambient thermal resistance (θ
JA
) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high maxi-
mum power dissipation exists, attention to thermal board design
is required. The value of θ
JA
may vary, depending on PCB material,
layout, and environmental conditions. The specified value of θ
JA
is based on a 4-layer, 4 in × 3 in, 2 1/2 oz copper board, as per
JEDEC standards. For more information, see the AN-772
Application Note, A Design and Manufacturing Guide for the
Lead Frame Chip Scale Package (LFCSP).
ESD CAUTION