Datasheet

ADP5020
Rev. 0 | Page 7 of 28
I
2
C TIMING SPECIFICATIONS
Table 6.
Parameter Min Max Unit Description
f
SCL
400 kHz SCL clock frequency
t
HIGH
0.6 μs SCL high time
t
LOW
1.3 μs SCL low time
t
SU,DAT
100 ns Data setup time
t
HD,DAT
1
0 0.9 μs Data hold time
t
SU,STA
0.6 μs Setup time for repeated start
t
HD,STA
0.6 μs Hold time for start/repeated start
t
BUF
1.3 μs Bus free time between a stop condition and a start condition
t
SU,STO
0.6 μs Setup time for stop condition
t
RISE
20 + 0.1C
B
300 ns Rise time of SCL/SDA
t
FALL
20 + 0.1C
B
300 ns Fall time of SCL/SDA
t
SP
0 50 ns Pulse width of suppressed spike
C
B
2
400 pF Capacitive load for each bus line
1
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
IHMIN
of the SCL signal) to bridge the undefined region of the SCL falling edge.
2
C
B
is the total capacitance of one bus line in picofarads (pF).
Timing Diagram
SDA
SCL
S
S = START CONDITION
Sr = START REPEATED CONDITION
P = STOP CONDITION
Sr P S
t
LOW
t
RISE
t
SU,DAT
t
HD,DAT
t
HIGH
t
FALL
t
FALL
t
SU,STA
t
HD,STA
t
SP
t
RISE
t
SU,STO
t
BUF
07774-003
Figure 3. I
2
C Interface Timing Diagram