Datasheet

ADP5020
Rev. 0 | Page 5 of 28
SWITCHING SPECIFICATIONS
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
SWITCHING FREQUENCY
CH1 f
SW1
Sync disabled 2.5 3 3.6 MHz
CH2 f
SW2
Sync disabled 2.5 3 3.6 MHz
SYNC CLOCK DIVIDER RATIO
RATIO
DIV
SYNC_9P6 = 1 3
RATIO
DIV
SYNC_19P2 = 1 6
SYNC CHARACTERISTICS
Frequency Range
f
SYNC1
9.6 MHz
f
SYNC2
19.2 MHz
Frequency Duty Cycle f
SYNCDUTY
40 50 60 %
Signal
DC Coupling Level
Low Level Input Voltage V
IL
0.3 × V
DD_IO
V
High Level Input Voltage V
IH
0.7 × V
DD_IO
V
DC Coupling V
SYNC
0 V
DD_IO
V
AC Coupling Level V
CAC-PP
Sine wave, peak-to-peak 0.5 1.0 V
DD_IO
V
AC Coupling Capacitor 10 nF
Input Current I
SYNC
SYNC_9P6 = 1, or SYNC_19P2 = 1 50 μA
DC-TO-DC CONVERSION SPECIFICATIONS, BUCK 1 REGULATOR
Table 3.
Parameter Symbol Conditions Min Typ Max Unit
OUTPUT VOLTAGE
Range
1
V
OUT1
3-bit range 2.5 3.7 V
Initial Accuracy
T
A
= 25°C, V
DD1
2
, V
OUT1
= 3.3 V, I
LOAD
= 20 mA
−1 +1 %
Total Accuracy V
DD1
3
, I
LOAD
= 50 mA to 600 mA −5 +4 %
VOUT1 REGULATION
Load Regulation I
LOAD
= 20 mA to 600 mA 0.2 %
Line Regulation V
DDA
= 1.8 V, V
DD1
2, 3
0.15 %
CURRENT
Maximum Output Current I
BK1MAX
V
DD1
3
, V
OUT1
= 2.5 V to 3.7 V 600 mA
Quiescent Current I
QBK1
I
LOAD
= 0 mA 4 6 mA
POWER
Low-Side Power nMOSFET R
DSON1
I
D
= 400 mA 175 250 mΩ
High-Side Power pMOSFET R
DSON1
I
D
= 400 mA 250 400 mΩ
SWITCH CURRENT LIMIT I
CL1
0.8 1.2 1.6 A
MINIMUM ON TIME t
MIN1
55 ns
MAXIMUM DUTY CYCLE D
MAX1
88 95 %
SOFT START TIME t
SS1
1.4 ms
C
OUT
DISCHARGE SWITCH ON RESISTANCE R
DIS1
0.7 1 1.3 kΩ
1
See (the BUCK1_VSEL register, Address 0x01) for details. Table 13
2
V
DD1
= 3.1 V to 5.5 V, I
LOAD
is less than 200 mA. For tight regulation, the supply voltage must be 0.6 V higher than the output voltage.
3
V
DD1
= 3.7 V to 5.5 V, I
LOAD
is more than 200 mA. For tight regulation, the supply voltage must be 1.2 V higher than the output voltage.