Datasheet

ADP5020
Rev. 0 | Page 24 of 28
PCB BOARD LAYOUT RECOMMENDATIONS
• Place the input and output capacitors, C1, C2, C3, C4, and
C5, as close as possible to the respective ADP5020 pin, and
make the grounding connection to the ADP5020 ground
pins as short as possible.
• Connect C3, C5, and C6 to the analog ground, and connect
C1, C2, and C4 to the power ground.
• Place the L1 and L2 inductors as close as possible to the
respective output pins.
• The power and analog ground planes are recommended to
keep the noise low. Use one layer for power ground and one
layer for analog ground. Tie the power and analog grounds
at a single point.
• Use wide traces to connect the inductor and the input and
output capacitors.
• Add the L3 inductor and the C8 capacitor, if needed, to
improve the LDO noise rejection at the switching fre-
quency of the Buck 1 regulator (3 MHz) because the LDO
PSRR typically degrades at higher frequencies. If switching
noise is not an issue, remove the L3 inductor.
EXTERNAL COMPONENT LIST
Table 19. Recommended External Components List
Reference
Designator Description Size Proposed Vendor Vendor Part No.
C1, C4 10 μF, X5R, 6.3 V, ±20% 0603 Murata GRM188R60J106M
C1, C4 10 μF, X5R, 6.3 V, ±20% 0603 Taiyo Yuden JMK107BJ106MA
C2 4.7 μF, X5R, 6.3 V, ±10% 0603 Murata GRM188R60J475K
C3 1.0 μF, X5R, 6.3 V, ±10% 0603 Murata GRM155R60J105K
C5 0.1 μF, X5R, 10 V, ±10% 0402 Murata GRM155R61A104K
C6 1.0 μF, X5R, 6.3 V, ±10% 0603 Murata GRM155R60J105K
L1 2.2 μH, DCR = 0.13 Ω, IDC = 1 A 2.5 mm × 1.8 mm × 1.2 mm Taiyo Yuden BRL2518T2R2M
L2 2.2 μH, DCR = 0.23 Ω, IDC = 0.53 A 2.0 mm × 1.2 mm × 1.0 mm Taiyo Yuden BRL2012T2R2M
R1, R2 10 kΩ, 1%, thick film resistor 0402 KOA Speer Electronics RK73H1ETTP1002F