Datasheet

ADP5020
Rev. 0 | Page 20 of 28
The application processor, together with the regulator power
good signal, controls the XSHTDN pin, as shown in Table 18 .
After a regulator is enabled and no failure condition is detected
(power good = 1 in Bits[3:1] of the REG_CONTROL_STATUS
register, Address 0x03), the level of the XSHTDN pin is con-
trolled by Bit 0 (FORCE_XS) in the REG_CONTROL_STATUS
register. Therefore, the application processor can write to this
register to gain control over the XSHTDN pin. However, if the
EN signal is high, the level on the XSHTDN pin depends on the
power good condition of the regulator.
Table 18. Truth Table
EN
Pin
I
2
C Regulator Enable
Power
Good
FORCE_XS
XSHTDN
Pin
0 0 0 X
1
0
0 1 X
1
0 0
0 1 0 1 0
0 1 1 1 1
1 X
1
1 X
1
1
1 X
1
0 X
1
0
1
X = don’t care.
POWER-UP/POWER-DOWN STATE FLOW
When the device is enabled, the UVLO circuit constantly monitors
the supply voltage. If the supply voltage falls below the V
UVLOF
threshold, typically 2.0 V, the regulators are immediately turned
off. All the internal analog circuits are then disabled to save power,
except the power-on reset (POR) circuit, which detects if the supply
voltage is dropping. If the supply voltage is higher than the POR
threshold, the POR circuit keeps the logic circuits operating
properly and retains the internal values of the registers. This
POR threshold is set to approximately 1.4 V.
If the supply voltage goes below the V
UVLOR
threshold, but not
below the POR threshold, the registers are preserved. If the supply
voltage returns to the normal operating level (above V
UVLOR
),
a new activation does not require initialization of the registers.
However, if the supply voltage goes below the POR level, the
device is held in reset state. When the input voltage resumes the
proper operating level, the host controller must reload the registers.
The additional current required to keep the POR monitoring
circuits alive during UVLO is estimated to be approximately 1 μA.
NO POWER
VDDx < V
POR
VDDx < V
POR
EN = LOW AND 1
2
C OFF
COMMAND
OR VDDx < V
UVLOF
I
2
C
COMMANDS
INTERNAL
RESET
EN = HIGH
STAND BY
TSD
STARTUP
SEQUENCER
NORMAL
OPERATION
SEQUENCE
END, AND ALL REGULATIONS ARE
POWER GOOD
VDDx > V
POR
LEVEL
EN = LOW
EN = LOW OR I
2
C OFF
COMMAND
OR VDDx < V
UVLOF
DEVICE ENABLED
(EN_ALL OR EN = HIGH)
07774-023
Figure 27. State Flow