Datasheet

ADP5020
Rev. 0 | Page 19 of 28
POWER-ON SEQUENCE USING THE I
2
C INTERFACE
When the EN pin is low, the regulator sequence is controlled by
the application processor sending I
2
C commands to control the
activation. When Bit 4 (EN_ALL) in the REG_CONTROL_
STATUS register (Address 0x03) is set to 1, the regulator sequence
is as follows:
1. Buck 1
2. LDO
3. Buck 2
This sequence can be factory programmed through fuses.
Unused regulators can also be fuse programmed to be turned
off during sequencing.
t
REG1
<50µs
t
REG2
t
REG3
t
XSHTDN
VDDx
V
UVLOR
V
UVLOF
POR
INTERNAL
POR
EN
BUCK 1
BUCK 2
LDO
XS
HTDN
I
2
C BUS
I
2
C SET/CLEAR
xxx_XSHTDN BITS
07774-021
Figure 25. Activation and Power Failure Conditions
EN
BK1_EN
= 1
BK2_EN
= 1
FORCE_XS
= 1
FORCE_XS
= 0
BK1_EN,
LDO_EN,
BK2_EN = 0
LD0_EN
= 1
I
2
C BUS
BUCK 1
BUCK 2
XSHTDN
LDO
07774-022
Figure 26. Individual Activation Through I
2
C Commands