Datasheet

ADP5020
Rev. 0 | Page 14 of 28
CONTROL REGISTERS
DEVICE ADDRESS
Following a start condition, the bus master must send the address
of the slave it is accessing. The slave address for the ADP5020 is
shown in Table 10. The Bit 0 defines the operation to be per-
formed. When this bit is set to Logic 1, a read operation is
selected. When this bit is set to Logic 0, a write operation is
selected.
Table 10. Slave Address
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 R/W
0 0 1 0 1 0 0 1 or 0
REGISTER MAP
Table 11.
Address Register Name D7 D6 D5 D4 D3 D2 D1 D0
0x00 Revision MAJ[2:0] MIN[2:0] OPT[1:0]
0x01 BUCK1_VSEL Reserved[7:3] BK1_VSEL[2:0]
0x02 BUCK2_LDO_VSEL BK2_VSEL[3:0] LDO_VSEL[3:0]
0x03
REG_CONTROL_STATUS BK1_EN BK2_EN LDO_EN EN_ALL
BK1_
PGOOD
BK2_
PGOOD
LDO_
PGOOD
FORCE_XS
0x04
OPERATIONAL_CONTROL Reserved SYNC_9P6 SYNC_19P2
SYNC_
AC
BK1_
XSHTDN
BK2_
XSHTDN
LDO_
XSHTDN
TSD
0x05
EN_CONTROL Reserved[7:2]
ENO_HIZ_
BAR
ENO_DRV
0x06 to
0x0F
Reserved
REGISTER DESCRIPTIONS
User Accessible Registers
Table 12. Revision Register, Address 0x00
Bit Bit Name Access Default Description
[7:5] MAJ[2:0] R N/A Major revision bits. Used to electronically ID the device version.
[4:2] MIN[2:0] R N/A Minor revision bits. Used to electronically ID the device version.
[1:0] OPT[1:0] R N/A Option bits. Used to electronically ID the option (multiple options on same device family).
Table 13. BUCK1_VSEL Register, Address 0x01
Bit Bit Name Access Default Description
[7:3] Reserved N/A N/A Reserved.
[2:0] BK1_VSEL[2:0] R/W Fuse
Sets the voltage output level of the Buck 1 regulator. Preloads on power-up with values
stored in fuses. Note that this value can be edited by the user in an application.
000 = 2.5 V.
001 = 2.8 V.
010 = 2.9 V.
011 = 3.0 V.
100 = 3.2 V.
101 = 3.3 V (default).
110 = 3.7 V.
111 = reserved.