Datasheet

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Power Management Unit

for Imaging Modules

ADP5020

Rev. 0

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FEATURES

Input voltage range: 2.4 V to 5.5 V

Low standby current: 1 μA

Switching frequency: 3 MHz

C interface

Synchronous Buck 1 regulator: 600 mA

Synchronous Buck 2 regulator: 250 mA

Low dropout regulator (LDO): 150 mA

Internal compensation

Internal soft start

Thermal shutdown

20-lead 4 mm × 4 mm LFCSP

APPLICATIONS

Digital cameras, handsets

Mobile TVs

TYPICAL APPLICATIONS CIRCUIT

VDD1

.4V TO 5.5

OUT1

2.5V TO 3.7V

OUT2

1.1V TO 1.8V

OUT3

1.8V TO 3.3V

EXT. FREQ

9.6/19.2MHz

DD_IO

1.7V TO 3.6

1µF

0.1µF

2.2µH

10µF

1µF

4.7µF

10µF

10kΩ 10kΩ

VDD2

VDD3

VDDA

VDD_IO

SDA

SCL

XSHTDN

EN/GPIO

DGND AGND

SYNC

VOUT3

PGND1

PGND2

VOUT1

VOUT2

SW2

SW1

07774-001

ADP5020

Figure 1.

GENERAL DESCRIPTION

The ADP5020 provides a highly integrated power solution that

includes all of the power circuits necessary for a digital imaging

module. It comprises two step-down dc-to-dc converters, one

LDO, and a power sequence controller. All dc-to-dc converters

integrate power pMOSFETs and nMOSFETs, making the system

simpler and more compact and reducing the cost. The ADP5020

has digitally programmed output voltages and buck converters

that can source up to 600 mA. A fixed frequency operation of

3 MHz enables the use of tiny inductors and capacitors. The buck

converters use a voltage mode, constant-frequency PWM control

scheme, and the synchronous rectification is implemented to

reduce the power loss. The Buck 1 regulator operates at up to

93% efficiency.

The ADP5020 provides high performance, reduces component

count and size, and is lower in cost when compared to conven-

tional designs.

The ADP5020 runs on input voltage from 2.4 V to 5.5 V and

supports one-cell lithium-ion (Li+) batteries. The high perfor-

mance LDO maximizes noise suppression. The ADP5020 can be

activated via an I

C® interface or through a dedicated enable input.

During logic-controlled shutdown, the input is disconnected

from the output source, and the part draws 1 μA typical from

the input source. Other key features include undervoltage lockout

to prevent deep-battery discharge and soft start to prevent input

current overshoot at startup. The ADP5020 is available in a

20-lead LFCSP.

Summary of content (28 pages)

PAGE 1
Power Management Unit for Imaging Modules ADP5020 FEATURES Input voltage range: 2.4 V to 5.5 V Low standby current: 1 μA Switching frequency: 3 MHz I2C interface Synchronous Buck 1 regulator: 600 mA Synchronous Buck 2 regulator: 250 mA Low dropout regulator (LDO): 150 mA Internal compensation Internal soft start Thermal shutdown 20-lead 4 mm × 4 mm LFCSP TYPICAL APPLICATIONS CIRCUIT VIN 2.4V TO 5.5V Digital cameras, handsets Mobile TVs 2.2µH VDD2 VOUT1 2.5V TO 3.
PAGE 2
ADP5020 TABLE OF CONTENTS Features .............................................................................................. 1 Undervoltage Lockout ............................................................... 13 Applications ....................................................................................... 1 Thermal Shutdown .................................................................... 13 Typical Applications Circuit............................................................
PAGE 3
ADP5020 FUNCTIONAL BLOCK DIAGRAM VDD3 VDD2 VDD1 VDDA SW1 XSHTDN RESET UVLO BUCK 1 VOUT1 VOUT1 PGND1 SCL I2C SDA SW2 BUCK 2 VDD_IO CONTROL LOGIC VOUT2 EN/GPIO PGND2 SYNC THERMAL SHUTDOWN LDO VOUT3 BUCK1_EN SEQUENCER HOUSEKEEPING BUCK2_EN LDO_EN DGND AGND Figure 2. Rev.
PAGE 4
ADP5020 SPECIFICATIONS TJ = −40°C to +125°C, VDDx = 3.6 V, VDD_IO = 1.8 V, unless otherwise noted. Table 1.
PAGE 5
ADP5020 SWITCHING SPECIFICATIONS Table 2. Parameter SWITCHING FREQUENCY CH1 CH2 SYNC CLOCK DIVIDER RATIO Symbol Conditions Min Typ Max Unit fSW1 fSW2 Sync disabled Sync disabled 2.5 2.5 3 3 3.6 3.
PAGE 6
ADP5020 DC-TO-DC CONVERSION SPECIFICATIONS, BUCK 2 REGULATOR Table 4. Parameter OUTPUT VOLTAGE Adjustable Range 1 Initial Accuracy Total Accuracy Load Regulation Line Regulation CURRENT Maximum Output Current Quiescent Current POWER Low-Side Power nMOSFET High-Side Power pMOSFET SWITCH CURRENT LIMIT MINIMUM ON TIME MAXIMUM DUTY CYCLE SOFT START TIME COUT DISCHARGE SWITCH ON RESISTANCE 1 Symbol Conditions Min VOUT2 4-bit range TA = 25°C, VDD2 = 3.6 V, VOUT2 = 1.2 V, ILOAD = 20 mA VDD2 = 2.
PAGE 7
ADP5020 I2C TIMING SPECIFICATIONS Table 6. Parameter fSCL tHIGH tLOW tSU,DAT tHD,DAT 1 tSU,STA tHD,STA tBUF tSU,STO tRISE tFALL tSP CB 2 1 2 Min Max 400 0.6 1.3 100 0 0.6 0.6 1.3 0.6 20 + 0.1CB 20 + 0.1CB 0 0.
PAGE 8
ADP5020 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 7. Parameter VDD1, VDD2, VDD3 SW1, SW2 VOUT1, VOUT2, VOUT3 VDD_IO EN, SCL, SDA, SYNC, XSHTDN Operating Temperature Range Ambient Junction Storage Temperature Range Lead Temperature Soldering (10 sec) Vapor Phase (60 sec) Infrared (15 sec) VESD Machine Model Range Human Body Model Range Charged Device Model θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Rating −0.
PAGE 9
ADP5020 VOUT1 14 VDD3 13 VOUT3 12 EN/GPIO 11 1 PGND2 ADP5020 2 VOUT2 BOTTOM VIEW (Not to Scale) 3 VDDA EXPOSED PAD VOUT2 2 4 AGND VDDA 3 5 SYNC AGND 4 17 SW1 16 PGND1 18 VDD1 19 VDD2 PIN 1 INDICATOR PGND2 1 ADP5020 TOP VIEW (Not to Scale) 13 VDD3 12 VOUT3 9 VDD_IO XSHTDN 10 8 SCL 6 6 DGND SDA 7 7 SDA Figure 4. Pin Configuration (Bottom View) 14 VOUT1 11 EN/GPIO DGND 8 SCL NOTES 1. EXPOSED PAD SHOULD BE CONNECTED TO PGND1 AND PGND2.
PAGE 10
ADP5020 TYPICAL PERFORMANCE CHARACTERISTICS VIN = 4.5 V, VOUT1 = 2.8 V, VOUT2 = VOUT3 = 1.8 V, IOUT = 100 mA, C4 = C1 = 10 μF, C2 = 4.7 μF, C3 = 1 μF, TJ = 25°C, unless otherwise noted. 3.5 95 3.3V 3.0V 3.0 90 2.0V 2.0 1.8V 1.5 VOUT1 (2.5V) VOUT2 (2.8V) VOUT3 (2.9V) VOUT4 (3.0V) VOUT5 (3.2V) VOUT6 (3.3V) VOUT7 (3.7V) 80 75 0 30 60 90 LOAD CURRENT (mA) 120 150 70 07774-006 0 Figure 6. LDO Load Regulation 100 200 300 400 LOAD CURRENT (mA) 500 Figure 9. Buck 1, Efficiency vs.
PAGE 11
ADP5020 VIN = 4.5 V, VOUT1 = 2.8 V, VOUT2 = VOUT3 = 1.8 V, IOUT = 100 mA, C4 = C1 = 10 μF, C2 = 4.7 μF, C3 = 1 μF, TJ = 25°C, unless otherwise noted. 0.90 BUCK 1 OUTPUT = 2V/DIV BUCK 2 OUTPUT = 1V/DIV 0.85 TIME = 5ms/DIV 0.75 0.70 EFF1 (1.1V) EFF2 (1.2V) EFF3 (1.3V) EFF4 (1.4V) EFF5 (1.5V) EFF6 (1.6V) EFF7 (1.7V) EFF8 (1.8V) 0.60 0.55 0.50 0 50 100 150 200 LOAD CURRENT (mA) 250 BUCK 2 ENABLE 300 07774-015 0.65 07774-012 EFFICIENCY (%) 0.80 Figure 15.
PAGE 12
ADP5020 VIN = 4.5 V, VOUT1 = 2.8 V, VOUT2 = VOUT3 = 1.8 V, IOUT = 100 mA, C4 = C1 = 10 μF, C2 =4.7 μF, C3 = 1 μF, TJ = 25°C, unless otherwise noted. LDO OUTPUT = 1V/DIV TIME = 50µs/DIV SW2 LDO BUCK 2 OUTPUT = 20mV/DIV SW2 = 5V/DIV TIME = 100ns/DIV 07774-030 07774-028 BUCK 2 Figure 18. LDO Startup Figure 20.
PAGE 13
ADP5020 THEORY OF OPERATION CIRCUIT OPERATION The buck converters use pMOSFET as the upper switch and nMOSFET as a synchronous rectifier. This synchronous rectification maintains high efficiency for a wide input and output voltage range. The voltage mode control architecture, which features a high frequency bandwidth, provides a fast load and line transient response. The Buck 1 regulator can deliver up to 600 mA with very tight regulation.
PAGE 14
ADP5020 CONTROL REGISTERS DEVICE ADDRESS Following a start condition, the bus master must send the address of the slave it is accessing. The slave address for the ADP5020 is shown in Table 10. The Bit 0 defines the operation to be per- formed. When this bit is set to Logic 1, a read operation is selected. When this bit is set to Logic 0, a write operation is selected. Table 10.
PAGE 15
ADP5020 Table 14. BUCK2_LDO_VSEL Register, Address 0x02 Bit [7:4] Bit Name BK2_VSEL[3:0] Access R/W Default Fuse [3:0] LDO_VSEL[3:0] R/W Fuse Description Sets the voltage output level of the Buck 2 regulator. Preloads on power-up with values stored in fuses. Note that this value can be edited by a user in an application. 0000 = 1.1 V. 0001 = 1.1 V. 0010 = 1.1 V. 0011 = 1.1 V. 0100 = 1.1 V. 0101 = 1.1 V. 0110 = 1.1 V. 0111 = 1.1 V. 1000 = 1.1 V. 1001 = 1.2 V (default). 1010 = 1.3 V. 1011 = 1.4 V.
PAGE 16
ADP5020 Table 15. REG_CONTROL_STATUS Register, Address 0x03 Bit 7 6 5 4 Bit Name BK1_EN BK2_EN LDO_EN EN_ALL Access R/W R/W R/W R/W Default 0 0 0 0 3 BK1_PGOOD R 0 2 BK2_PGOOD R 0 1 LDO_PGOOD R 0 0 FORCE_XS R/W 0 Description 1 = turns on the Buck 1 regulator. If the EN pin is high, the sequencer is ignored. 1 = turns on the Buck 2 regulator. If the EN pin is high, the sequencer is ignored. 1 = turns on the LDO regulator. If the EN pin is high, the sequencer is ignored.
PAGE 17
ADP5020 POWER-UP/POWER-DOWN SEQUENCE SEQUENCER DEFAULT POWER-ON SEQUENCE WITH EN PIN The sequencer is enabled after a low-to-high transition of the enable pin (EN). When EN is low or programmed as an output, the sequencing is controlled and timed by the application processor via the I2C commands. Figure 22 shows the default regulator sequencing after a low-tohigh transition of the EN pin. The regulator order is factory programmed and can be changed for specific applications.
PAGE 18
ADP5020 Activation Waveforms VDDx VUVLOR POR INTERNAL POR EN I2C BUS I2C SEQUENCER REGISTERS PROGRAMMING EN_ ALL = 1 EN_ ALL = 0 tREG1 POK tREG2 BUCK 1 POK tREG3 LDO POK tXSHTDN 07774-019 BUCK 2 XSHTDN Figure 23. Regulators Are Activated by I2C Command VDDx POR INTERNAL POR EN I2C BUS I2C SEQUENCER REGISTERS PROGRAMMING tREG1 POK BUCK 1 tREG2 POK tREG3 LDO POK tXSHTDN 07774-020 BUCK 2 XSHTDN Figure 24.
PAGE 19
ADP5020 POWER-ON SEQUENCE USING THE I2C INTERFACE 1. 2. 3. When the EN pin is low, the regulator sequence is controlled by the application processor sending I2C commands to control the activation. When Bit 4 (EN_ALL) in the REG_CONTROL_ STATUS register (Address 0x03) is set to 1, the regulator sequence is as follows: Buck 1 LDO Buck 2 This sequence can be factory programmed through fuses. Unused regulators can also be fuse programmed to be turned off during sequencing.
PAGE 20
ADP5020 The application processor, together with the regulator power good signal, controls the XSHTDN pin, as shown in Table 18. After a regulator is enabled and no failure condition is detected (power good = 1 in Bits[3:1] of the REG_CONTROL_STATUS register, Address 0x03), the level of the XSHTDN pin is controlled by Bit 0 (FORCE_XS) in the REG_CONTROL_STATUS register. Therefore, the application processor can write to this register to gain control over the XSHTDN pin.
PAGE 21
ADP5020 APPLICATIONS INFORMATION Peak inductor current is calculated in the following equation: POWER GOOD STATUS The ADP5020 constantly monitors the operating conditions. When a regulator is activated, it checks if the output voltage level is above 80% (the power good threshold) of the nominal level for that output. If the output voltage does not reach the power good threshold, one of the three power good status bits in the REG_CONTROL_STATUS register (Address 0x03) is cleared.
PAGE 22
ADP5020 ADP5020 LDO INPUT FILTER SW1 VBATT C1 10µF VOUT1 VOUT1 1 2 × π × L3 × C8 (3) where L3 = 250 nH, assuming that fLC = 1 MHz and C8 = 100 nF. The inductor must be able to withstand the LDO load current, including the overload condition, which is limited to 400 mA. Rev. 0 | Page 22 of 28 3.3V C6 10µF The filter resonance frequency is determined by the following equation: f LC = L1 2.2µH BUCK 1 LDO INPUT FILTER L3 VDD3 C8 0.1µF LDO VOUT3 2.8V C3 1µF Figure 28.
PAGE 23
ADP5020 LAYOUT RECOMMENDATIONS APPLICATIONS SCHEMATIC ADP5020 VDD1 VBATT C4 10µF SW1 GND BUCK 1 INPUT POWER SUPPLIES VDD2 VOUT1 VOUT1 +VIS C1 10µF PGND1 L2 2.2µH BUCK 2 VOUT2 VDD_IO VDDIO C5 0.1µF SDA SCL SCL VOUT3 +VIO C3 1.0µF –VIO SYNC EN/GPIO XSHTDN DGND XSHTDN AGND 07774-027 GPIO/EN –VCORE R2 10kΩ SDA SYNC C2 4.7µF PGND2 LDO R1 10kΩ +VCORE SW2 OUTPUT POWER RAILS C6 1.0µF –VIS VDD3 VDDA PROCESSOR INTERFACE L1 2.2µH Figure 29.
PAGE 24
ADP5020 • PCB BOARD LAYOUT RECOMMENDATIONS • • • Place the input and output capacitors, C1, C2, C3, C4, and C5, as close as possible to the respective ADP5020 pin, and make the grounding connection to the ADP5020 ground pins as short as possible. Connect C3, C5, and C6 to the analog ground, and connect C1, C2, and C4 to the power ground. Place the L1 and L2 inductors as close as possible to the respective output pins. • • The power and analog ground planes are recommended to keep the noise low.
PAGE 25
ADP5020 OUTLINE DIMENSIONS 0.60 MAX 4.00 BSC SQ 0.60 MAX 15 PIN 1 INDICATOR 20 16 1 PIN 1 INDICATOR 3.75 BSC SQ 0.50 BSC 2.65 2.50 SQ 2.35 EXPOSED PAD (BOTTOM VIEW) 5 10 1.00 0.85 0.80 12° MAX 0.80 MAX 0.65 TYP 0.30 0.23 0.18 SEATING PLANE 0.50 0.40 0.30 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
PAGE 26
ADP5020 NOTES Rev.
PAGE 27
ADP5020 NOTES Rev.