Datasheet

ADP3654
Rev. 0 | Page 3 of 12
SPECIFICATIONS
V
DD
= 12 V, T
J
= −40°C to +125°C, unless otherwise noted.
1
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
SUPPLY
Supply Voltage Range V
DD
4.5 18 V
Supply Current I
DD
No switching 1.2 3 mA
UVLO
Turn-On Threshold Voltage V
UVLO_ON
V
DD
rising, T
J
= 25°C, see Figure 3 3.8 4.2 4.5 V
Turn-Off Threshold Voltage V
UVLO_OFF
V
DD
falling, T
J
= 25°C, see Figure 3 3.5 3.9 4.3 V
Hysteresis 0.3 V
DIGITAL INPUTS (INA, INB)
Input Voltage High V
IH
See Figure 2 2.0 V
Input Voltage Low V
IL
See Figure 2 0.8 V
Input Current I
IN
0 V < V
IN
< V
DD
−20 +20 μA
Internal Pull-Up/Pull-Down Current 6 μA
OUTPUTS (OUTA, OUTB)
Output Resistance, Unbiased VDD = PGND 80 kΩ
Peak Source Current See Figure 14 4 A
Peak Sink Current See Figure 14 −4 A
SWITCHING TIME
OUTA and OUTB Rise Time t
RISE
C
LOAD
= 2.2 nF, see Figure 2 10 25 ns
OUTA and OUTB Fall Time t
FALL
C
LOAD
= 2.2 nF, see Figure 2 10 25 ns
OUTA and OUTB Rising Propagation Delay t
D1
C
LOAD
= 2.2 nF, see Figure 2 14 30 ns
OUTA and OUTB Falling Propagation Delay t
D2
C
LOAD
= 2.2 nF, see Figure 2 22 35 ns
Delay Matching Between Channels 2 ns
1
All limits at temperature extremes guaranteed via correlation using standard statistical quality control (SQC) methods.
TIMING DIAGRAMS
INA,
INB
OUTA,
OUTB
t
D1
t
RISE
10%
90%
10%
90%
V
IH
V
IL
t
D2
t
FALL
09054-002
Figure 2. Output Timing Diagram
NORMAL OPERATIONUVLO MODE
OUTPUTS DISABLED
V
DD
V
UVLO_ON
V
UVLO_OFF
UVLO MODE
OUTPUTS DISABLED
0
9054-003
Figure 3. UVLO Function