Datasheet

ADP3654
Rev. 0 | Page 11 of 12
In addition to the gate charge losses, there are also dc bias
losses, due to the bias current of the driver. This current is
present regardless of the switching.
P
DC
= V
DD
× I
DD
The total estimated loss is the sum of P
DC
and P
GATE
.
P
LOSS
= P
DC
+ (n × P
GATE
)
where n is the number of gates driven.
When the total power loss is calculated, the temperature
increase can be calculated as
ΔT
J
= P
LOSS
× θ
JA
Design Example
For example, consider driving two IRFS4310Z MOSFETs with a
V
DD
of 12 V at a switching frequency of 300 kHz, using an
ADP3654 in the SOIC_N_EP package.
The maximum PCB temperature considered for this design is 85°C.
From the MOSFET data sheet, the total gate charge is Q
G
= 120 nC.
P
GATE
= 12 V × 120 nC × 300 kHz = 432 mW
P
DC
= 12 V × 1.2 mA = 14.4 mW
P
LOSS
= 14.4 mW + (2 × 432 mW) = 878.4 mW
The SOIC_N_EP thermal resistance is 59°C/W.
ΔT
J
= 878.4 mW × 59°C/W = 51.8°C
T
J
= T
A
+ ΔT
J
= 136.8°C ≤ T
JMAX
This estimated junction temperature does not factor in the
power dissipated in the external gate resistor and, therefore,
provides a certain guard band.
If a lower junction temperature is required by the design,
the MINI_SO_EP package can be used, which provides a
thermal resistance of 43°C/W, so that the maximum junction
temperature is
ΔT
J
= 878.4 mW × 43°C/W = 37.7°C
T
J
= T
A
+ ΔT
J
= 122.7°C ≤ T
JMAX
Other options to reduce power dissipation in the driver include
reducing the value of the V
DD
bias voltage, reducing switching fre-
quency, and choosing a power MOSFET with smaller gate charge.