Datasheet

ADP3654
Rev. 0 | Page 10 of 12
Figure 16 shows an example of the typical layout based on the
preceding guidelines.
09054-016
Figure 16. External Component Placement Example
Note that the exposed pad of the package is not directly con-
nected to any pin of the package, but it is electrically and
thermally connected to the die substrate, which is the ground
of the device.
PARALLEL OPERATION
The two driver channels present in the ADP3654 device can be
combined to operate in parallel to increase drive capability and
minimize power dissipation in the driver.
The connection scheme is shown in Figure 17. In this configura-
tion, INA and INB are connected together, and OUTA and
OUTB are connected together.
Particular attention must be paid to the layout in this case to
optimize load sharing between the two drivers.
INA
VDD
V
DD
PGND
ADP3654
OUTA
OUTBINB
NC
NC
1
3
8
7
6
5
A
B
2
4
V
DS
0
9054-017
Figure 17. Parallel Operation
THERMAL CONSIDERATIONS
When designing a power MOSFET gate drive, the maximum
power dissipation in the driver must be considered to avoid
exceeding maximum junction temperature.
Data on package thermal resistance is provided in Table 2 to
help the designer with this task.
There are several equally important aspects that must be
considered, such as the following:
• Gate charge of the power MOSFET being driven
• Bias voltage value used to power the driver
• Maximum switching frequency of operation
• Value of external gate resistance
• Maximum ambient (and PCB) temperature
• Type of package
All of these factors influence and limit the maximum allowable
power dissipated in the driver.
The gate of a power MOSFET has a nonlinear capacitance
characteristic. For this reason, although the input capacitance
is usually reported in the MOSFET data sheet as C
ISS
, it is not
useful to calculate power losses.
The total gate charge necessary to turn on a power MOSFET
device is usually reported on the device data sheet under Q
G
.
This parameter varies from a few nanocoulombs (nC) to several
hundred nC, and is specified at a specific V
GS
value (10 V
or 4.5 V).
The power necessary to charge and then discharge the gate of a
power MOSFET can be calculated as:
P
GATE
= V
GS
× Q
G
× f
SW
where:
V
GS
is the bias voltage powering the driver (VDD).
Q
G
is the total gate charge.
f
SW
is the maximum switching frequency.
The power dissipated for each gate (P
GATE
) still needs to be
multiplied by the number of drivers (in this case, 1 or 2) being
used in each package, and it represents the total power dissi-
pated in charging and discharging the gates of the power
MOSFETs.
Not all of this power is dissipated in the gate driver because part
of it is actually dissipated in the external gate resistor, R
G
. The
larger the external gate resistor is, the smaller the amount of
power that is dissipated in the gate driver.
In modern switching power applications, the value of the gate
resistor is kept at a minimum to increase switching speed and
minimize switching losses.
In all practical applications where the external resistor is in the
order of a few ohms, the contribution of the external resistor
can be neglected, and the extra loss is assumed in the driver,
providing a good guard band to the power loss calculations.