Datasheet

REV. A
ADP3331
–7–
V
OUT
V
IN
+
ADP3331
FB
OUT
ERR
ON
OFF
SD
GND
IN
C2
0.47␮F
C1
0.47␮F
+
E
OUT
R4
R1
R2
R
NR
C
NR
R3
Figure 3. Noise Reduction Circuit
Output Voltage
The ADP3331 has an adjustable output voltage that can be set by
an external resistor divider. The output voltage will be divided by
R1 and R2, and then fed back to the FB pin. Refer to Figure 3.
For the output voltage to have the lowest possible sensitivity to
temperature variations, it is important that the parallel resistance
of R1 and R2 be as close as possible to 230 kW:
RR
RR
k
12
12
230
¥
+
=W
(1)
Also, for the best accuracy over temperature, the feedback voltage
should set for 1.204 V:
V
R
RR
V
OUT FB
2
12+
Ê
Ë
Á
ˆ
¯
˜
=
(2)
Where V
OUT
is the desired output voltage and V
FB
is the virtual
band gap voltage. Note that V
FB
does not actually appear at the
FB pin due to loading by the internal PTAT current.
Combining the above equations and solving for R1 and R2
results in the following formulas:
R
V
V
k
OUT
FB
1 230=
Ê
Ë
Á
ˆ
¯
˜
W
(3)
R
V
V
k
FB
OUT
2
230
1
=
-
Ê
Ë
Á
ˆ
¯
˜
W
(4)
The output voltage can be adjusted to any voltage from 1.5 V to
11.75 V. For example, Table I shows some representative feed-
back resistor values for output voltages in the specified range.
Table I. Feedback Resistor Selection
V
OUT
(V) R1 (1%) R2 (1%) R3 (1%)
1.5 243 kW 1.00 MW 34.8 kW
1.8 340 kW 698 kW
2.2 422 kW 511 kW
2.7 511 kW 412 kW
3.3 634 kW 365 kW
5 953 kW 301 kW
9 1.00 MW 154 kW 97.6 kW
Note that at output voltages above 5.2 V and below 1.6 V, non-
standard resistor values or the addition of a resistor to the divider
network is required to achieve the best performance. For output
voltages below 1.6 V, select a standard resistance value for R2 and
then calculate the value of R1:
R
V
V
R
OUT
FB
112=-
Ê
Ë
Á
ˆ
¯
˜
¥
(5)
For output voltages above 5.2 V, select a standard resistance for
R1, and calculate the value of R2:
RR
V
VV
FB
OUT FB
21=¥
-
Ê
Ë
Á
ˆ
¯
˜
(6)
After selecting values for R1 and R2, calculate the value of R3
needed to maintain the 230 k impedance:
Rk
RR
RR
3 230
12
12
=-
¥
+
Ê
Ë
Á
ˆ
¯
˜
W
(7)
Using standard values, as shown in Table I, will sacrifice some
output voltage accuracy.
Output Current Limit
The ADP3331 is short-circuit protected by limiting the pass
transistor’s base drive current. The maximum output current is
limited to about 300 mA.
Thermal Overload Protection
The ADP3331 is protected by its thermal overload protection
circuit against damage due to excessive power dissipation.
Thermal protection limits the die temperature to a maximum of
165∞C. Under extreme conditions (i.e., high ambient tempera-
ture and power dissipation) where the die temperature starts to
rise above 165∞C, the output current will be reduced until the
die temperature has dropped to a safe level.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, the device’s power dissipation should be externally
limited so that the junction temperature will not exceed 125∞C.
Chip-on-Lead
The ADP3331 uses a patented Chip-on-Lead package design to
ensure the best thermal performance in a SOT-23 footprint. In a
standard SOT-23, most of the heat flows out of the ground pin.
The Chip-on-Lead package uses an electrically isolated die
attach, which allows all the pins to contribute to heat conduction.
This technique reduces the thermal resistance to 190∞C/W on a
2-layer board compared to >230∞C/W for a standard SOT-23
lead frame. Figure 4 shows the difference between the standard
SOT-23 and the Chip-on-Lead lead frames.