Datasheet

Data Sheet ADP322/ADP323
Rev. A | Page 15 of 24
THEORY OF OPERATION
The ADP322/ADP323 triple LDO are low quiescent current, low
dropout linear regulators that operate from 1.8 V to 5.5 V on
VIN1/VIN2 and VIN3 and provide up to 200 mA of current from
each output. Drawing a low 250 A quiescent current (typical) at
full load makes the ADP322/ADP323 ideal for battery-operated
portable equipment. Shutdown current consumption is typically
100 nA. Optimized for use with small 1 µF ceramic capacitors,
the ADP322/ADP323 provide excellent transient performance.
Internally, the ADP322 consists of a reference, three error ampli-
fiers, three feedback voltage dividers, and three PMOS pass
transistors. Output current is delivered via the PMOS pass device,
which is controlled by the error amplifier. The error amplifier
compares the reference voltage with the feedback voltage from the
output and amplifies the difference. If the feedback voltage is lower
than the reference voltage, the gate of the PMOS device is pulled
lower, allowing more current to flow and increasing the output vol-
tage. If the feedback voltage is higher than the reference voltage, the
gate of the PMOS device is pulled higher, allowing less current
to flow and decreasing the output voltage.
0.5V
REF
OVERCURRENT
V
OUT1
V
OUT2
V
OUT3
VIN1/VIN2
GND
EN1
VBIAS
VIN3
EN3
EN2
0.5V
REF
OVERCURRENT
0.5V
REF
OVERCURRENT
INTERNAL BIAS
VOLTAGES/CURRENTS,
UVLO AND THERMAL
PROTECT
SHUTDOWN
VOUT1
SHUTDOWN
VOUT2
SHUTDOWN
VOUT3
09288-041
+
+
+
Figure 43. ADP322 Internal Block Diagram
The ADP323 differs from the ADP322 except in that the output
voltage dividers are internally disconnected and the feedback
inputs of the error amplifiers are brought out for each output.
0.5V
REF
OVERCURRENT
VOUT1
VOUT2
VOUT3
FB1
FB2
FB3
VIN1/VIN2
GND
EN1
VBIAS
VIN3
EN3
EN2
0.5V
REF
OVERCURRENT
0.5V
REF
OVERCURRENT
INTERNAL BIAS
VOLTAGES/CURRENTS,
UVLO AND THERMAL
PROTECT
SHUTDOWN
VOUT1
SHUTDOWN
VOUT2
SHUTDOWN
VOUT3
0
9288-055
+
+
+
Figure 44. ADP323 Internal Block Diagram
The output voltage can be set using the following formulas:
V
OUT
= 0.5 V(1 + R1/R2) + (FB
IN
)(R1)
V
OUT2
= 0.5 V(1 + R3/R4) + (FB
IN
)(R3)
V
OUT3
= 0.5 V(1 + R5/R6) + (FB
IN
)(R5)
The value of R1, R3, R5 should be less than 200 k to minimize
errors in the output voltage caused by the FBx pin input
current. For example, when R1 and R2 each equal 200 k, the
output voltage is 1.0 V. The output voltage error introduced by
the FBx pin input current is 2 mV or 0.20%, assuming a typical
FBx pin input current of 10 nA at 25°C.
The ADP322 is available in multiple output voltage options
ranging from 0.8 V to 3.3 V.
The ADP322/ADP323 use the EN1/EN2 and EN3 pins to
enable and disable the VOUT1/VOUT2/VOUT3 pins under
normal operating conditions. When the EN1/EN2 and EN3
pins are high, VOUT1/VOUT2/VOUT3 turn on; when the
EN1/EN2 and EN3 pins are low, VOUT1/VOUT2/VOUT3 turn
off. For automatic startup, the EN1/EN2 and EN3 pins can be
tied to VBIAS.
0
9288-145
ADP323
VBIAS
VOUT1
GND
VBIAS
1µF
OFF
ON
EN1
OFF
ON
EN2
OFF
ON
EN3
+
1µF
+
LDO 1
EN LD1
VBIAS
VBIAS
VOUT2
1µF
+
LDO 2
EN LD2
VOUT3
1µF
+
LDO 3
EN LD3
2
.5
V
TO
5.5V
VIN1/VIN2
VIN3
1µF
+
1.8
V
TO
5.5V
1.8
V
TO
5.5V
1µF
+
FB1
R2
R1
FB2
R4
R3
FB3
R6
R5
Figure 45. ADP323 Application Circuit Diagram